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ADC31JB68: How to setup the ADC and FPGA for 500 MHz sample data

Part Number: ADC31JB68

Hi,

We developed and FMC card based on ADC31JB68 ADC. I have the following setup my ADC input freq is 5 MHz but I only see  25 samples which means the ADC is sampling at 125 MHz. I need 4 times the samples with 500 MHz sampling freq.

I am using ZCU102 Eval kit from Xilinx and have the lane rate of 5 Gbps and using two lanes per ADC. And as per the device data sheet will only get one octet per lane and my clock settings are 

ADC DEV Clock - 500 MHz

ADC SYSREF Clock - 15.625 MHz

FPGA CORE Clock - 125 MHz

FPGA REF Clock - 500 MHz

FPGA SYSREF Clock - 15.625 MHz

Am I doing any thing wrong. How do I get all the samples for 500 MHz sampling freq ?

Rgds,

Stephen

  • Hi Stephen,

    I think that the FPGA REF Clock might be to fast. Have you tried a 125 MHz FPGA REF clock?

    My suggestion would be to run the ramp pattern, and reduce the speed (divide by 4) of the FPGA REF clock.

    Please take a look at the link below where a customer had a "similar" issue with Xilinx JESD IP.

    http://e2e.ti.com/support/data-converters/f/73/p/869539/3219309#3219309

    Best Regards,

    Dan

  • Hi Dan,

    I looked at the link that you provided that does not resolve my issue. I want to sample the ADC at 500 MHz and capture all the samples in the FPGA. 

    Also what is frequency of the Ramp?

    Rgds,

    Stephen

  • Hi Stephen,

    How are you initiating the JESD IP? Have you ensured that the parameters are set in accordance with the ADC31JB68 datasheet [L (2), M (1), F (1), S (1), K (32), etc...See page 26. Default values are in parenthesis.]?

    Page 42 and 43 of the datasheet show the registers required to enable the ramp pattern (step size is adjustable). This might not be necessary if you are seeing the sinewave input though.

    Since you are not capturing the required samples, I think there may still be an issue on the FPGA side. Have you tried adjusting the FPGA ref clock rate?

    Are you able to provide screenshots of the waveforms?

    Best Regards,

    Dan

  • Hi Dan,

    I am initializing the parameters over the AXI Interface and I read back the registers to make sure they are set right. Please see the register values below

    JESD204B ILA_SUPPORT                     Reg 0x08 = 0x00000001
    JESD204B SCRAMBLING                      Reg 0x0C = 0x00000000
    JESD204B SYSREF                               Reg 0x10 = 0x00010000
    JESD204B OCTETS                               Reg 0x20 = 0x00000000
    JESD204B FRAMES                               Reg 0x24 = 0x0000001F
    JESD204B SUBCLASS_MODE              Reg 0x2C = 0x00000001
    JESD204B LANES                                  Reg 0x28 = 0x000000FF
    JESD204B successfully initialized.
    JESD204_PHY successfully initialized.

    I tried using 125 MHz for both GTH REF Clock and CORE Clock. There is no difference I am only capturing 25 samples.

    Let me ask you this, what are teh clock values on your setup to capture samples @ 500 MHz.

    Rgds

    Stephen

     

  • Hi Stephen,

    Can you please check the register addresses? It looks like your register address values do not line up with the datasheet.

    For our evaluation platform (ADC31JB68EVM and TSW14J56EVM), we use a 250 MHz FPGA reference clock. This is for an Altera (Intel) based FPGA.

    Best Regards,

    Dan

  • Hi Dan,

    The registers I mentioned are for the Xilinx JESD Block. I believe you have an example for ZCU102 which is what I used to develop my test program. 

    I will try setting the REF Clock to 250 MHz, what is the core clock set to ?

    Rgds,

    Stephen

  • Hi Stephen,

    Ok, thanks for clearing that up. I am not certain as to what the FPGA JESD IP core registers should be set to. Perhaps the Xilinx support team could assist with this?

    Please use a core clock of 500 MHz.

    Best Regards,

    Dan

  • Hi Dan,

    I tried 250 MHz for both REF Clock and CORE Clock and it did not work.

    Rgds,

    Stephen

  • Hi Stephen,

    In the TSW14J10EVM User's Guide, it says this about the FPGA clocks.

    "The REFCLK and Core clock are determined by the following lane rate conditions:
    REFCLK = Lane rate / 10, and Core clock = Lane rate / 10 when lane rate is between 1 G and 3.2 G.
    REFCLK = Lane rate / 20 and Core clock = Lane rate / 40 when lane rate is between 3.2 G and 10.3125 G*."

    That means, you should be using...REFCLK= 5 Gbps/20 = 250 MHz, Core CLK = 5 Gbps/40 = 125 MHz.

    Also, perhaps this thread might help as well.

    https://e2e.ti.com/support/data-converters/f/73/t/896563

    Best Regards,

    Dan

  • Hi Dan,

    Can you please post the register settings for the ADC on your eval kit? Or is it possible to lend a Eval kit so that we can compare the two boards?

    Also what clock are you using to register the data coming out of the JESD204B block?

    Rgds,

    Stephen

  • Hi Stephen,

    The ADC31JB68EVM uses the power-up defaults for the register settings. See attached or datasheet for reference.

    ADC31JB68EVM_Defaults.csv

    As for the clock used for the JESD block, I am not 100% certain. It should be an integer of the sampling clock (probably 125 MHz or 250 MHz).

    Best Regards,

    Dan

  • Thanks Dan,

    Its now working we had the bits in the wrong order.

    Rgds,

    Stephen