Hi,
We developed and FMC card based on ADC31JB68 ADC. I have the following setup my ADC input freq is 5 MHz but I only see 25 samples which means the ADC is sampling at 125 MHz. I need 4 times the samples with 500 MHz sampling freq.
I am using ZCU102 Eval kit from Xilinx and have the lane rate of 5 Gbps and using two lanes per ADC. And as per the device data sheet will only get one octet per lane and my clock settings are
ADC DEV Clock - 500 MHz
ADC SYSREF Clock - 15.625 MHz
FPGA CORE Clock - 125 MHz
FPGA REF Clock - 500 MHz
FPGA SYSREF Clock - 15.625 MHz
Am I doing any thing wrong. How do I get all the samples for 500 MHz sampling freq ?
Rgds,
Stephen