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about aic3204 3254 DAC Gian

C Gain

Hello

who can give me an example to explain this table, I am really confused.

Thank you

Bo Li

3 Replies

  • Hi, Bo,

    Sorry for the delay. Did you get this figured out?

    Basically, what it means is we can adjust the audio quality/supply current consumption. If you can sacrifice some audio quality, you can save some supply current, thus extending battery life.

    -d2

  • In reply to Don Dapkus:

    Hi Don

    As refered the example code "Texas Instruments\AIC3254 CS\DATA\EVM\AIC3254\PLAYBACK\PLAYBACK_LOW_POWER.TXT". I know how to do the compensation when choose PTM and understand the concept of compencetion wiht PTM choosing.

    Thank you

    Bo Li .

    ......
    # Set the DAC PTM mode to PTM_P1
    w 30 03 08 08
    #
    # Power up HPL/HPR and LOL/LOR drivers
    w 30 09 3C
    #
    # Unmute HPL/HPR driver, -5dB + 14dB for PTM_P1 compensation
    w 30 10 09 09
    #
    # Unmute LOL/LOR driver, -5dB + 14dB for PTM_P1 compensation
    w 30 12 09 09
    ........

     

  • In reply to Don Dapkus:

    Hi Don

    I want to demonstate ADC and DAc Gain settings. I expected that when input is full scale, the output is full scale too, but when input is 120mv(RMS), the output reahes 500mv(RMS), I don't know where signal are amplified, in adc channle or dac channel? I atteched my script, please help.

    I tested DRC function by providing different level sine signals to IN1L,R, the output is not restricted to -24db full scale, it still can be up to full scale 500mv(RMS). Any thing I misunderstand the DRC function? or any code I missed to write? please help to explain.

    Thank you

    Bo Li

     

     Gian Test
    ###############################################
    # Software Reset
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Initialize the device through software reset
    w 30 01 01
    #
    ###############################################

     

    ###############################################
    # Clock Settings
    # ---------------------------------------------
    # The codec receives: MCLK = 11.2896 MHz,
    # BLCK = 2.8224 MHz, WCLK = 44.1 kHz
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # NADC = 2, MADC = 2,
    # dac OSR=64,
    w 30 0b 82
    w 30 0c 82
    w 30 0d 00 40
    #
    # NADC DIVIDER POWER DOWN, ADC_CLK SAME AS DAC_CLK, AOSR=64
    W 30 14 40
    #
    ###############################################

    ###############################################
    # Signal Processing Settings
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Set the DAC Mode to PRB_P8 (STERO, DRC, 4 BQ, Interpolation B, RC=8)
    # DRC not enabled yet(see reg68 default)
    w 30 3c 08
    #
    # Set the ADC Mode to PRB_R8(STERO, AGC, 3 BQ, AOSR 64, Decimation Filter B,RC=4)
    # AGC not enabled yet(see req86,94 default)
    w 30 3d 08
    #
    ###############################################

    ################################################
    # ROUT ADC TO DAC
    ################################################
    # Select Page 0
    w 30 00 00
    #
    # Stereo ADC output is routed to Stereo DAC input, BDIV_CLKIN=DAC_CLK
    w 30 1D 10
    #
    ###############################################


    ###############################################
    # Initialize Codec
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # Disable weak AVDD in presence of external
    # AVDD supply
    w 30 01 08
    #
    # Enable Master Analog Power Control
    w 30 02 00
    #
    # Set the input common mode to 0.9V. (0x00 is default, full chip common mode 0.9)
    w 30 0a 00
    #
    # Select ADC PTM_R3
    w 30 3d 03
    #
    # Set the input powerup time to 3.1ms (for ADC)
    w 30 47 32
    #
    # Set the REF charging time to 40ms
    w 30 7b 01
    #
    ###############################################


    ###############################################
    # Recording Setup
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # Route IN1L to LEFT_P with 10K input impedance
    w 30 34 40
    #
    # Route Common Mode to LEFT_M with impedance of 10K
    w 30 36 40
    #
    # Route IN1R to RIGHT_P with input impedance of 10K
    w 30 37 40
    #
    # Route Common Mode to RIGHT_M with impedance of 10K
    w 30 39 40
    #####################################################################
    # Unmute Left MICPGA, Gain selection of 0dB to make channel gain 0dB.
    w 30 3b 00
    #
    # Unmute Right MICPGA, Gain selection of 0dB to make channel gain 0dB.
    w 30 3c 00
    #---------------------------------------------------------------------
    # above code will be useless, if AGC is used. Let it here, it is original code of TI sample.
    ######################################################################
    # Select Page 0
    w 30 00 00
    #
    # Power up LADC/RADC
    w 30 51 c0
    #
    # Unmute LADC/RADC
    w 30 52 00
    ################################################


    ###############################################
    # Playback Setup
    ###############################################
    # Select Page 1
    w 30 00 01
    #
    # De-pop
    w 30 14 25
    #
    # Route LDAC/RDAC to HPL/HPR
    w 30 0c 08 08
    #
    # Route LDAC/RDAC to LOL/LOR
    w 30 0e 08 08
    #
    # Set the DAC PTM mode to PTM_P3,4
    w 30 03 00 00
    #
    # Power up HPL/HPR and LOL/LOR drivers
    w 30 09 3C
    #
    # Unmute HPL/HPR driver, 0db driver gain
    w 30 10 00 00
    #
    # Unmute LOL/LOR driver, 0db driver gain
    w 30 12 00 00
    #
    # Power up HPL/HPR and LOL/LOR drivers
    #w 30 09 3C
    #
    # Select Page 0
    w 30 00 00
    #
    # DAC => 0dB , L and R
    w 30 41 00 00
    #
    # Power up LDAC/RDAC , route Left channel Left Audio interface data and Right channel Right Audio Interface data
    w 30 3f d6
    #
    # Unmute LDAC/RDAC
    w 30 40 00
    #
    ###############################################

     

     

     

     for DRC test, following code added after above code

    ###############################################
    # DRC Setup, this part originally copied from "C:\Program Files\Texas Instruments\AIC3254 CS\DATA\EVM\AIC3254\DRC\DRC_PRB_25.TXT"

    #to make sure DRC filter parameters are active, paramters are written to buffer-A and buffer-B as well.
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # DAC => DRC Enabled for both channels,
    # Threshold = -24 db, Hysteresis = 0 dB
    w 30 44 7c
    #
    # DRC Hold = 0 ms,
    # Rate of Change of Gain = 0.5 dB/Fs'
    w 30 45 00
    #
    # Attack Rate = 1.9531e-4 dB/Frame,
    # DRC Decay Rate =2.4414e-5 dB/Frame
    w 30 46 B6
    #
    # go to page 44
    w 30 00 2C
    #
    # DAC Adaptive filter enabled, Buffer-B in Using, Buffer-A in control interface, Buffer not switched in next frame
    w 30 01 06
    #
    # Go to Page 46 Buffer-A
    w 30 00 2E
    #
    # DRC HPF
    w 30 34 7F AB 00 00 80 55 00 00 7F 56 00
    #
    # DRC LPF
    w 30 40 00 11 00 00 00 11 00 00 7F DE 00
    #
    # go to page 44
    w 30 01 2c
    #
    # DAC Adaptive filter enabled, Buffer-A in Using, Buffer-B in control interface, Buffer not switched in next frame
    w 30 01 04
    #
    # go to page 64
    w 30 00 40
    #
    # DRC HPF
    w 30 34 7F AB 00 00 80 55 00 00 7F 56 00
    #
    # DRC LPF
    w 30 40 00 11 00 00 00 11 00 00 7F DE 00
    #
    # go to page 44
    w 30 01 2c
    #
    # DAC Adaptive filter enabled, Buffer-A in Using, Buffer-B in control interface, Buffer switched in next frame
    w 30 01 05
    #

    ###############################################