I have not yet looked at your project, but I will.
In the mean time, to support additional sample rates, your application:
1. needs to indicate in the Type 1 Format Descriptor the sample rates that you support (from what you say in your email, you likely have done this correctly, since the host does send at alternate sample rates).
2. need to handle the 'set sample rate' command from the host. This command should result in setting-up the acg for the correct frequency. If you're seeing only 44.1kHz I2S, this likely has not been done.
3. modify the SOF interrupt handler so that the closed-loop acg algorithm tweaks the setting based on the current sample rate. Again, if you're seeing only 44.1kHz I2S, this likely has not been done.
4. will likely have to make the audio sample buffer larger, in order to hold the additional samples - this becomes apparent only when you listen to the audio.
You may also have to send something to your DAC so that it knows the sample rate.
Do you think that you have done all of this? It may take me a few days to take a look at your application to see what's missing.
One last thing: a couple of posters have indicated that if you set the buffer size too big, the DMA doesn't work correctly. I haven't tracked this down, but if what you are hearing is bad audio, you might want to look for forum postings regarding a maximum buffer size.
Thanks for your reply.I'll get some tips above ^ ^I'm hardware developer. So I do not know the software.However, by analyzing the source code for many days,The description was complete update. But .....Word clock as measured by the oscilloscope in the 44.1KHZ did not change.- SoftPll.c# define SOF_EXPECTED_DELTA 11289# define SOF_EXPECTED_REMAINDER 600# define ACG_N 0x006A4B20# define ACGDCTL_VALUE 0x10# define ACGCTL_VALUE 0x44# define UPDATE_PERIOD 4This entry manually change it is possible to change the sampling.However, I am the host PC when changing the sampling in the application of thisI want to be handled by the TAS1020.Change the sampling rate from the host PC,USB logic analyzer is shown as packet data is changing.This viewpoint, TAS1020B interrupt part of the firmware seems to be in need of improvement.Tas1020 Firmware Development Kit, or I could find some reference source alone is very difficult due to insufficient resources.Reference source is needed to improve interrupt.Let's modify based on what has given you.Thank you for your help. ^ ^Have a nice day.
The application in the TAS1020B FDK is written for an EVM that uses an AC97 codec. With an AC97 codec, the clock to the codec is always at 48kHz, no matter whether the audio sample rate is 32kHz, 44.1kHz, or 48kHz; that's why you don't see any adjustment to the ACG settings as a function of the sample rate that the host sends.
However, with an I2S codec, the clock must be a function of the sample rate, so when the TAS1020B receives a 'set sample rate' command, it needs to 'remember' the commanded rate, modify the ACG register settings so that the appropriate output rate is generated, and modify the softPll algorithm to close the feedback loop at that new sample rate.
lt was a reference source for ac97.I understand. ^ ^Different sample rate to be applied,See the source code after the other will try to improve.Thanks in advice.Have a nice day ^ ^
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