I'm using the TLV320AIC3106 codec on the LogicPD OMAP-L138 Zoom Development kit and I have run into some complications.
For my system to work properly, the AIC3106 has to be configured for a sampling rate of exactly 9600 Hz, this is the main goal. However, my problem is that the MCLK, WCLK and BCLK lines are only physically connected to the transmit section of the McASP of the C6748 DSP. The implication is that the codec cannot be setup as the master, since the generated clock lines cannot reach the receive section of the McASP (unless I mod the dev kit).
To mitigate this, the McASP has to be the master and generate the bit clock and frame sync, which is then transmitted on the ACLKX and AFSX pins, respectively. The transmit and receive section of the McASP should obviously be configured exactly the same. The problem I am having now is that the dividers of the McASP are only integer values and the input clock from the PLL is simply AUXCLK (i.e. the crystal oscillator), which is 24 MHz. The target value for the bit clock is:
BCLK = 9600 Hz * number of bits per frame
So for example, in DSP mode the number of bits is 32 and BCLK should therefore be 9600 * 32 = 307200 Hz. Since the McASP dividers is only integers, this cannot be achieved with a AUXCLK of 24 MHz. One possible way of achieving the correct bit clock is to play around with the number of bits per frame, so one possible option would be to configure the McASP for 3 slots of 16 bits each, and with an initial delay of 2 bit clocks, which should give a (3*16 + 2) = 50 bits per frame. With 50 bits per frame the bit clock will be as follows:
BCLK = 9600 Hz * 50 = 480000 Hz
This can actually be achieved by using a McASP division factor of 50. This finally brings me to my question:
How can I setup the AIC3106 codec to use the first two 16-bit slots (taking into account the 2 clock bit delay) of the TDM transmission from the McASP, and then simply ignore the last slot? Is this possible at all?
Your help would be greatly appreciated!
In DSP mode, the AIC3106 will always just look at the first two time slots regardless of how many bit clocks there are. You can set the BCLK offset in the TDM register 10 on Page 0. If you set the offset to 2, the AIC3106 will wait two BCLK's then clock in the next two channels ignoring any additional BCLKs until the next frame.
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