Hi community member,
Please let me confirm the following question.
Does this device(AIC3254) has a limitation of input frequency accuracy?
i.e. Would you please teach me the rule of input frequency in detail?
* I know that the maximum frequency was described in SLAA408 as "Maximum TLV320AIC3254 Clock Frequencies".
Now, customer used the signal which was generated by USB OSC block in DSP.
They would like to change this signal to use the signal which is generated by crystal(12MHz).
So, they would like to know whether the signal has a limitation to use.
If you have any questions, please let me know.
According to the data sheet Recommended Operating Conditions table (page 6), MCLK has a maximum input frequency of 50MHz at a DVdd > 1.65V, and 25MHz at DVdd > 1.26V. So the only thing they would need for 12MHz is to recalculate the clock dividers.
In reply to David Lines:
Hi David,Thank you for your comment.Regarding to your comment, they only need for 12MHz is to recalculate the clock dividers. So, it does not mind the accuracy of input clock.i.e. there is not problem for the operation to use the clock which has Frequency stability of +/- 5000ppm for inputting signal for AIC3254.Is my understanding correct?If no, would you please teach me the required specification of input clock in case of 12MHz?
In reply to Kaka:
Would anyone please provide answer for my question by end of today in US time?
I must inform to customer this ASAP. So, It would be very helpful if anyone could answer for my question.
Would anyone please provide answer for my question?
If there is jitter in the clock it might degrade the SNR preformance of the device and can tolerate upto ~100ps rms jitter. However if PLL is used, it will tolerate much larger jitter. If there a time shift in the mclk frequency, it will show up as a shift in the output frequency.
In reply to Vins:
Thank you for response.
Would you please the jitter tolerance of MCLK in case of using the internal PLL of AIC3254?
If you do not have a data of this, it is OK that the data is reference data.
* Customer's board will make system clock from input MCLK by using the internal PLL of AIC3254.
I do not have the information of PLL's jitter tolerance. If the customer insist, we can dig in and provide it towards end of next week only.
OK. I was requested to provide this data from customer.
So, would you please evaluate to get to data?
Consulted R&D team on this and the recommendation is to have a clock source of max jitter of 100ps with or without PLL enabled.
Thank you for confirming.
I will inform this information to customer as below. Would you please check whether there is not problem for my understanding(comment) just in case?
If must keep the specification of AIC3254 on datasheet without reference to use the internal PLL, they need to prepare a clock source which is the max jitter of 100ps.
Also, if I provide the specification of Clock source which customer will use, would you please confirm whether there is any problem to use it for inputting AIC3254?
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