I have only the codec and a uC on a short I2C connection, and I'd like to bit-bash the I2C control interface faster than 400 kHz (peak).The I2C specs in the data sheet (SLAS510B–FEBRUARY 2007–REVISED DECEMBER 2008) say low- and full-speed, with minimum HD-STA, SU-STA, and SU-STO of >= 0.9us. I would like the actual device setup and hold times and minimum pulse widths, hoping that they're better than full speed limits. The transistors in the codec should be capable of 6ns setup and hold like the data interface, but there may be other logic limitations.
I'm also considering using a
push-pull drive from the uC on SDA and SCL for the I2C bits that it masters. This would give faster rise times on SCL and SDA. The uC can avoid contention by appropriate I/O control.
Does the codec have a open-drain
(low-clock-stretching) transistor on SCL? If the codec never stretches SCL, then the uC could always drive SCL.
SCL does get stretched when needed by the AIC3104 and we have not had good results in trying to run faster than full-speed (400 kHz). You will almost certainly have problems if you try to go faster. If you check the data sheet our setup time is actually slightly longer than the I2S spec for full-speed.
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