TLV320AIC3254: Unexpected Gain Causing Clipping

Expert 6030 points

Part Number: TLV320AIC3254


See below from customer on customer.  Can you help explain the gain and why clipping may be occurring with 50 mV input?

As I mentioned, there seems to be a 12-15dB gain in the system I can't account for.  The primary reference block diagram is the "analog routing diagram" Fig 2-1 of the app note.

Here's what I have: 

* Datasheet specs ~ 500mVrms full-scale at the ADC (numerous references, e.g. Datasheet THD spec sec 8.9, app note references for 0.9v common mode ~ VCM, etc)

* Input distortion using Hilbert program begins at ~10-30mVpp (freq dependent).  Result is oscillation and spurious phase inversion at output, with 150mVpp output prior to distortion when measured by oscilloscope on LINE_OUT

* Result is the same at input 1p (our primary input), but also at input

2 and 3 (differential or single-ended, if Vpp is adjusted to be constant).  Return to single-ended mode from here on, rule out DC bias.

* Assumed this clipping is either over-driven input or digital saturation of filters.

* Simplified program to "pass-through" block diagram (ADC input, DSP-A/DSP-D transfer block, DAC output).  No change to clip point.  No filters, filter saturation is unlikely.

* Built tone generator program for 1khz tone direct to output (no DSP-A/DSP-D transfer), with no input.  Set digital oscillator amplitude to 1.0.  No distortion or clipping, output amplitude is about 350mVpp and very clean.  Output overdrive is unlikely since this is well past the clip point we saw with our Hilbert program.

* Based on this, I believe the problem is input gain, and the oscillation merely is due to reconstruction filter and/or output interpolator interacting with clipped data.  Ignore oscillation for now and focus on input gain.

* Return to pass-through program to investigate gain settings.  Setting input PGA gain resistors to 40Kohm to IN1 for INL_P, 40Kohm to VCM1 for INL_R (INR unused).  Input drive now clips at 50mVpp.  Retain 40k PGA from here on.

* Changes to different INL_N (external DC bias, mic input, etc) do not improve the situation.  Clip point is asymmetric, clipping more on positive peaks than negatives (when overlay input vs output on scope).

IN1L_P must have a built in bias of VCM that I didn't see in app note. 

Leave INL_N to VCM from here on.

* Change input volume control to -12dB.  Output amplitude down to ~50 mV prior to clip, with quantization noise apparent on oscilloscope connected to LINE_OUT.  Returning to 0dB input volume control.

* Changed output volume control to -12dB.  Similar results above. 

Results suggest clip is prior to the ADC proper, at the analog buffer (PGA or earlier).

* Enabled input AGC, target to -24dBFS.  Significant distortion (looks like harmonic distortion, but FFT not available - may be intermodulation).  AGC  returned to 0dB and disabled.  Results suggest AGC is performed digitally after the ADC has clipped.

* Repeated 40kohm "pass-trhough" program with different values for oversampling ratio (AOSR/DOSR) on the ADC and DAC.  Minimal difference to clip point, although the character of what we see on LINE_OUT changes, particularly the quantization noise.  This suggests the AOSR and DOSR do not in general provide gain.

* Tried new program using the sidetone circuit to go from PGA directly to LINE_OUT amp.  No DSP blocks in block diagram, no ADC or DACs.  This program only adjusts the register banks.  Clip point still at 50mVpp for 40k PGA resistor.  This also suggests the clip is somewhere at- or near the PGA

Bottom line is, by walking the signal from the output backwards, we see that the only improvement occurred with changing PGA resistor settings. 

Best result is 50mV at the input.  This is consistent with a change from default 10kohm to 40kohm resulting in a change of clip from 10mV to 50mV.  This is why I suggested the 1:10 voltage divider at the input of the TLV320AIC chip.  We see approx 10 dB of unaccounted for gain before we reach the spec'd 500mVpp ADC clip point.

3 Replies

  • Hello,

    Could you provide the actual register configuration? Additionally, could you provide the codec schematic portion? This would help us to get more information about this issue.

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • In reply to Luis Fernando Rodríguez S.:


    Thank you for provide the schematic and the registers settings.

    I have few comments about them.

    - Schematic:
    - Please route the unused analog inputs to 0.47uF capacitors to GND.
    - Separate the digital and analog ground pins into two different ground planes (digital gnd and analog gnd). Both planes must be routed with a 0-ohm resistor or a ground trace.

    - Registers settings:
    - Could you provide the BCLK, MCLK and WCLK values that you are using? We normally recommend to use an AOSR = DOSR = 128. This provides the best performance.
    - Do you have a PPS process flow? I mean, it seems that your code is using PurePath Studio, do you have the process flow file?

    Best regards,
    Luis Fernando Rodríguez S.
  • In reply to Luis Fernando Rodríguez S.:


    I checked the process flows that you sent. It seems that you are using decimator and interpolator blocks for high simple rates such 192KHz and 176.4KHz. However, the process flow is being configured for lower sampling rates (8KHz and 16KHz). For lower sampling rates, you would require to use Dec4xIn and Int8xOut. Could you try with these blocks?

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.