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PCM3008: How can we avoid the issue of click noise?

Part Number: PCM3008

Dears:

From our datasheet of PCM3008 it will generate some noise and according to test it happens indeed, could we use some method to avoid the click noise?

Since we will use PCM3008 to replace AK4554VT.

Pls. kindly give some advice, thanks a lot!

Test:

  • Hi, Lian,

    As the datasheet mentions, this noise issue is an expected behavior of the device when the clocks provided to the codec are not synchronized. The only way to avoid the noise would be by ensuring the clocks to be synchronized at all times. If the asynchronous behavior is expected in the end-system as part of an initialization process, maybe you can suggest to keep the device in powerdown (assert /PDAD and /PDDA pins to low) until clocks are stable.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • In reply to Diego Melendez:

    Hi Diego:

    Could you kindly give some method to test and control the clocks synchronized?

    Btw, there is other issue as follows:

    From the datasheet the BCK is 64, 48 or 32 clocks of BCK? 

  • In reply to Lian Wu:

    Hi Diego:

    Below pictures are LRCK and MCLK, are they OK?

  • In reply to Lian Wu:

    Hi, Lian,

    Thanks for the feedback. Even if the clock rates relations are matching between LRCK and MCLK, the synchronization might not be good if the clocks are not generated from the same source (in general, the host device). In order to ensure the synchronization between LRCK and MCLK, LRCK should be generated from MCLK at some point. Could you please confirm if LRCK is generated from the MCLK in your system?

    About the BCK/LRCK relationship, the device expects either 32, 48 or 64 bit clocks per word clock. As long as any of these relations are met, the device will operate properly.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • In reply to Diego Melendez:

    Hi Diego:

    Customer confused with the below information:

    PCM3008 does not need a specific phase relationship between LRCK and system clock, but does require the synchronization of LRCK and system clock.

    If the relationship between system clock and LRCK changes more than ±4 BCK during one sample period

    Could you give us some steps of testing synchronization? Or some diagram?

    Many thanks!

    Regards!

    Luck Wu