Audio Converters Forum - Recent Threads

ADAU1442 SPDIF Lock Bit

Bernd Nimmrichter — Mon, 17 Jun 2013 09:46:50 GMT

When connecting a SPDIF Signal to the ADAU1442 the first time after power on on there is a nasty click.

Question: Is it possible to access the SPDIF Lock Bit inside the DSP program to trigger a delayed UnMute ?

LMC567 External clocking

Andrew Safronov — Mon, 17 Jun 2013 12:33:48 GMT

Hi!

May I clocking a LMC567 from external clock? For example, from microcontroller which clocking from quartz generator.

Thanks!

TAS5548EVM does not connect

Philip Nubile — Mon, 17 Jun 2013 17:33:47 GMT

Received my TAS5548EVM. Installed all the software. When I press the connect button I get an error message "could not connect to device". It is connected with the USB cable and the blue and green LEDs on the module are illuminated.

Any special driver installation required here? I am using windows XP sp3

LM49450 - Sequencing Of Supply Voltage Rails

Brian Gosselin — Tue, 18 Jun 2013 01:47:55 GMT

Hi Team,

This question is in regards to the LM49450..

There is the supply voltage (Vdd, LSVdd), headphone supply voltage (CPVdd, HPVdd), digital core supply voltage (DVdd), and the digital IO supply voltage (IOVdd).

Is there a sequencing criteria for these supply voltages?

Best regards,
Brian Gosselin

TLV320AIC11: could this be used to drive a Piezo speaker

Madhuri Akkenepalli — Tue, 18 Jun 2013 05:20:37 GMT

My customer has a question regarding this part. Can this codec's class-D output can drive a piezo speaker. They are currently redesigning a platform that was based on the BS300 using a new Cortex M3 paired up with a codec and piezo driver.

Please advise on techniques/app notes to drive the Piezo speaker.

Thank you

TLV320AIC33 slave mode

SAKHO — Tue, 31 May 2011 22:04:49 GMT

hi,

we would use the AIC33 in slave mode (AIC33 slave and DSP master). And at the same time, we must use BCLK to generate the internal audio master clock. We tried this configuration, but we can not make audio playback. Does this configuration is feasible? what parameters and what register should really take into consideration??

Thank you in advance

Sakho

TLV320AIC34 and TLV320AIC3105 queries

Gitesh Bhagwat — Wed, 12 Jun 2013 13:07:19 GMT

Hi,

We have the following queries:

1. TLV320AIC3105:

We are using the TI audio codec, AIC3105 in one of our boards. We are observing a significant attenuation in the frequency response of the codec below 200Hz and also at the high end around 18KHz. Please let us know if the codec has a flat frequency response over the audio frequency range (20Hz – 20KHz).

2. TLV320AIC34:

We have the following queries regarding the AIC34 codec.

Each block of the codec (A or B) has two mic inputs and one microphone detect (MICDET). How can we connect this MICDET to both the mic inputs?
Can we use the line outputs of the codec in single ended mode? If so, do we need to ground the negative input or can we leave it no connected?
We need to interface the line outputs to 3.5mm stereo jacks in single ended mode. In that case what is the ac coupling capacitor that has to be used to connect the line outs to stereo jacks?
Does the codec support jack/headset detection on line outputs?

Regards,

Gitesh

PCM3070 - Audio Mixing configuration

Winnefred Kinggam — Tue, 11 Jun 2013 09:52:45 GMT

Hello,

I am planning to implement the below circuit for audio mixing using PCM3070,

Inputs : HPL_A_1, HPL_A_2, HPL_B_1, HPL_B_2

Output : LOR ( pin 23 )

For this, I am trying to configure PCM3070 registers with MSP430 via SPI.

I would like to know what are the registers that are necessary for this application.

I know that its all available in the datasheet, but i would be nice if TI experts could pin down the necessary registers for this application.

Would be useful for others too.

DIX4192

Max Forster — Mon, 10 Jun 2013 06:44:58 GMT

Hi,

I have two questions regarding the configuration of DIX4192.

First questions is related to register 15 (Receiver Status Register 3) and 'OSLIP Error'. I use Port A to output DIR data in "Master Mode" with RXCLKO as clock source (Register 3: 0x29, and register 4: 0x08), I do not use Port B (but I set register 5: 0x41 to mute Port B, and register 6: 0x0). Now, if I enable OSLIP interrupt in register 17 (= 0x01) and read the status from it (register 0x15) I got an OSLIP error indicated all the time. My receiver part works, but I am a little bit confused as I understand the description in register 15 that this error occurs only if I use a slave configuration of the Port A or B for output DIR. Do I miss something?

Second one is regarding the 'Receiver Loss of Lock' (LOL) option in register 0x0E. In my application I have a receiver which will locked to transmitter (also DIX4192) and play audio (192kHz), it might happen that somebody removes the cable totally so that I will lose lock. If user plugs calbe in again it should work as before very quick. In most cases that works very well with activated "LOL" option (my configuration of register 0x0E in that case is: 0x19), but sometimes it will result in toggling nLock on receiver. I measured already RXCLKO which looks good, but that state of toggling nLock (which you can, of course, hear also in audio) will not go to an stable state even after a relly long time. If I do not use the "LOL" option it looks good for me, but it takes more time to activate audio again after loss of lock.

Best regards,

Max

Mic input noise with AIC3204 and AIC3254

kurt57633 — Mon, 04 Oct 2010 14:35:52 GMT

Hello All,

I need some assistance in reducing the mic input noise we’re hearing with the TLV320AIC3254 and TLV320AIC3204. It sounds like white noise. I’m using a single-ended mic configuration with 10K input resistors and a headset. It’s not a super high level of noise, but it is noticeable. Our gain is set to 35 dB.

To isolate the problem, I put the microphone in ADC bypass using mixer amplifiers mode (5.3.2 in datasheet). This routes the microphone level signals to the headphone output fully bypassing the ADC and DAC. I hear the white noise even if I remove the microphone, or ground out the mic input. Therefore, I don’t think it is the microphone generating the noise. I do get the least amount of noise by selecting the lowest mic bias voltage generated by the LDO.

The DAC performance is excellent. When I output a sine wave from the I2S interface it sounds great. When I output zero to the I2S DAC interface, the headphones are absolutely quiet. Therefore, I’ve narrowed the problem down to the analog input (PGA and mic bias).

So far we’ve used the AGC with the noise threshold (74 dB) to gate the noise. This sounds good if you speak into the mic at high enough volumes to overcome the noise threshold. Some quieter talkers have trouble with this, and if we lower the noise threshold anymore to accommodate them, the noise starts to cut in and out again.

We have all the unused inputs capacitively coupled and grounded.

Any ideas would be appreciated. I’ve been through all the register settings and cannot seem to find anything else to do programmatically. I’m not sure the 3254 DSP functions with pure path studio would help eliminate the noise either.

Thank you,
kurt

PCM1680 clock and layout

Sammy Peiren — Sat, 15 Jun 2013 14:51:02 GMT

Hi, I'm using a PCM1680 with a variable, non-standard sample rate. My digital audio processors require an input frequency of 144 times the sample rate and I want to use 512 times oversampling for the PCM1680. To achieve this I thought of using the CDCE913 programmable clock, it can output both frequencies and they are in sync.

I was looking at the datasheet for the PCM1680 and it shows a recommended layout, however the clock path is not shown. Do you have any advice on the layout of the CDCE913? Since it supplies the clock for both my digital section and the PCM1680 it is not strictly part of either of those sections. Wouldn't the split in the ground plane be bad for EMC if I lay out the clock lines to both sides? What return path should I provide for the 144xfs clock?

I've included an image of the recommended layout. My changes are in red. I also need an additional LDO to get the required voltages for the CDCE913.

How to control PCM codec : TLV320AIC1106 EVM?

Eddy Lee — Sun, 16 Jun 2013 07:59:17 GMT

HI,

I have some problems.

TLV320AIC1106 using Mic input(1KHz,sine)(ch1) but EAR output is only DC level(ch2).

I think, AIC1106 is very simple Hardware type codec and EVM is not need GUI program.

Only USB driver detection and then operation.

Please your comment.

Eddy Lee(eddy.lee@avnet.com)

lm49350 GUI

Erick Farias — Fri, 14 Jun 2013 23:30:32 GMT

hello everyone:

I've been working with the evaluation board of LM49350 Audio codec that has an user interface board, Searching deep in the web I found a GUI for the Codec that is the version 1.5 , and i don't know if it is the last version, can someone tell me if there is a new one?

now when I configured the Codec to use the ADC and the DAC the signal just as a loop and taking out through the class D amplifier and the signal has a lot noise ( sounds like white noise ) ! . I think it is a bug on the GUI or the order that I set up the settings, can someone post the correct procedure for initialize the codec to sampling at 48Khz and the DAC to output at the same frequency.

thanks !

PCM1808 - About a power supply (VCC & VDD) sequence

hideto kanemaru — Thu, 06 Jun 2013 14:55:00 GMT

Is there the recommended power supply (VDD & VCC)sequence?

My customer thinks about the following case(1 , 2 , 3).

Does PCM1808 not malfunction with each case?

================

<case1>

VDD and VCC do power supply ON at the same time.

-------------

<case2>

“VCC = ON , VDD = ON” => “VCC = ON , VDD = OFF (stop SCKI)”

*Only VDD is power off.

-------------

<case3>

“VCC = ON , VDD = OFF” => “VCC = ON , VDD = ON (start SCKI)”

*VDD is power ON again

================

LM49350

Jes��s Zendejas — Fri, 14 Jun 2013 19:09:18 GMT

Hi everybody,

I am trying to find out the reason of a white noise, which it is being generated when I do the following configuration:

-The input MCLK pin is connected to the output of a 12MHz oscillator.

-My PLL_1 settings are as follows: PLL1_CLK_SEL = 0, PLL1_M = 4, PLL1_N = 32, PLL1_N_MOD = 0, PLL1_P1 = 24, PLL1_P2 = 24. (M = 2.5, N = 32, N_MOD = 0, P = 12.5).

-With the PLL configuration described above I think I am getting 12.288MHz.

-After that I configure the input clocks of ADC and DAC with the PLL1_OUTPUT2 and with the PLL1_OUTPUT1 respectively.

-The audio quality required is 48K stero with 16-bit per sample.

-I want to sample the input signals of Right MIC and connect this output to the DAC and after that to the Class-D amplifier, all of this because I want to perform some DSP effect to this signal.

-So, I configure the ADC_INPUT with MICR_ADCR and MICL_ADCL inputs.

-ADC_BASIC_OSR = 128 of oversampling, ADC_CLK_SEL = 3, similar configuration for DAC.

-ADC_CLK_DIV and DAC_CLK_DIV = 1

-DAC_INPUT = ADC_L and ADC_R

-CLASS_D_OUTPUT = DACR_LS and DACL_LS

Regards,

Jesus Zendejas

PCM3168A question

Michael Jordan — Fri, 14 Jun 2013 16:10:04 GMT

I have researched the posts that I could find on this subject, and I understand that the answer is probably no. I have to ask before I put all of the work into this, though.

Are there any header/development files available for this particular codec?

If anyone can assist I would be very appreciative.

Thank you

Michael

LM49350 as I2S Master

Erick Farias — Tue, 23 Apr 2013 16:25:56 GMT

hello everyone

I've been reading the reference manual of the LM49350 audio codec and I couldn't identify the configuration that makes the codec work as the I2S master device , for my application I only need to receive data from the MCU to the codec, Can anybody help me ?

Vioce effects such as Echo, Reverb, Delay

Wattanasit Pimpao — Fri, 14 Jun 2013 07:27:18 GMT

I am looking for a chip that can provide me vioce effects such as Echo, Reverb, Delay. Please advice me some.

AIC34 High Power Outputs.

Mushtaq Syed — Thu, 13 Jun 2013 01:09:08 GMT

Hi:

On page 50 of SLAS538A (data sheet for AIC34 audio codec), it is stated in the first paragraph "The user should first program the type of output configuration being used in page 0, register 14, to allow the device to select the optimal power-up scheme to avoid output artifacts." However, register 14 deals with headset/button press detection. Based on this, my interpretation is that what is described in register 14 applies to the high power outputs HPLOUT and HPROUT that are used with headsets. Regsiter 14 does not apply to high power outputs HPLCOM and HPRCOM. Is my interpretation correct?

Thanks a lot!

Cheers,

Mushtaq

1000 points FFT Audio compensation

uMin — Fri, 07 Jun 2013 21:33:38 GMT

Hi,

My customer is working on a stereo home audio system and has an idea to add an fixed compensation circuit to it. They want to add a fixed 1000 or 1024 points FFT coefficients to the audio signal to obtain a flat frequency response curve across the audio band. The audio source is in analog, and the output can be either analog or digital.

Not sure is it feasible to implement with any audio dac and purepath studio ?

Regards,

CM.

Audio Input not working (PCM2900c)

David de — Tue, 11 Jun 2013 14:51:05 GMT

I just figured out that I have a PCM2900c chip on the PCM2906cevm board. I am having a problem recording audio, it doesn´t detect the noise from the mic.

Thanks

TLV320DAC3101 settings for playing 48KHz 16bit stereo audio stream

Ganesha LD — Tue, 11 Jun 2013 11:27:24 GMT

Hi,

We are trying to play 48kHz 16bit STEREO audio stream using TLC320DAC3101.

I am able to hear the voice in speakers (very very feable, but seemingly correct), but with a very loud hissing noise along with the audio.

Please look in to the following register settings that I have done and suggest anything that I have missed OR wrongfully done.

I have checked the BCLK and WCLK pins, and I can see the correct clock output at the pins (BCLK = 1.536MHz and WCLK = 48000Hz) and audio data is coming on to DIN pin from processor.

Please look into the attached audio schematics.

Clock input -> MCLK PIN

/* ============================
   SETTINGS CALCULATION :

   PLL_CLK_IN = 11.1111 MHz OR 11111111 Hz
   PLL_CLK = 86016000 = (R * J.D) / P
   P = 1, R = 1, J = 7, D = 7414

   CODEC_CLK_IN = PLL_CLK

   NDAC = 2, MDAC = 7, DOSR = 128

BCLK = (48000 * 16 * 2) Hz; WCLK = 48000Hz
=============================================

Reg 1-> 0x01 //Soft reset the Control registers

Reg 4 -> 0x07; //PLL_CLKIN=MCLK && CODEC_CLKIN=PLL_CLK

Reg 5 -> 0x01 << 7 | 0x01 << 4 | 0x01 << 0; //PLL ON && P = 1, R = 1

Reg 6 -> 7; // J = 7

Reg 7 -> 0x1C; // D Val MSB

Reg 8 -> 0xF6; // D val LSB

Reg 11 -> 0x80 | 0x07; // NDAC POWER ON | NDAC_VAL

Reg 12 -> 0x80 | 0x002; // MDAC POWER ON | MDAC_VAL

Reg 13 -> 0x00; //DOSR MSB(9:8)

Reg 14 -> 0x80; //DOSR LSB(7:0)

Reg 27 -> (0x01 << 3) | (0x01 << 2) | (0x03 << 4); //BCLK is OUTPUT && WCLK is OUTPUT; 32 bit interface (16 + 16)

Reg 29-> 0x01; //BDIV_CLKIN = DAC_MOD_CLOCK

Reg 30-> (0x01 << 7) | (0x04 << 0); //BCLK N-divider is powered up && BDIV_N = 4; So, BCLK = (48000 * 16 *2)Hz

Reg 63-> (0x01 << 7) | (0x01 << 4) | (0x01 << 6) | (0x01 << 2) | (0x01 << 0); //DAC Power ON && DAC Data Path = Left-Right data respectively

Reg 64-> 0x00; // DAC NOT muted

Reg 65-> 0x00; // Left-DAC 0dB gain

Reg 66-> 0x00; // Right-DAC 0dB gain

//--------------------------------------------------------------------

/ /PAGE 1 Settings

Reg 0-> 0x01 // Go to PAGE 1

Reg 32-> (0x01 << 7) | (0x01 << 6) | (0x3 << 1); //Class D driver Power ON

Reg 35-> (0x01 << 6) | (0x01 << 2); //DAC-L DAC-L routed to mixer Amplifiers Left and Right

Reg 38-> (0x01 << 7); // Analog Volume routed to Class D Left, Volume MAX

Reg 39-> (0x01 << 7); // Analog Volume routed to Class D Right, Volume MAX

Reg 42-> (0x01 << 2) | (00 << 3); //Class-D driver LEFT is NOT muted

Reg 43-> (0x01 << 2) | (00 << 3); //Class-D driver RIGHT is NOT muted

Reg 0-> 0x00; // Go to PAGE 0

============================================================================

Please help me in this regard..

Thanks,

-Ganesh

Configuring AIC3204 for 8Khz Mono ADC and also DAC

DARAM — Sat, 01 Jun 2013 11:05:20 GMT

Hi
im using aic3204 on a ezDSP C5515 based design board,in the event of trying to capture audio from the codec and feeding that pcm data to speex open source codec

i doubt the codec configurations done i use a electret (2 wired ) micro phone usually it requires mic bias and im using to LDO for that purpose my configuration code as follows

/* ------------------------------------------------------------------------ *

* Configure AIC3204 *
* Set of Values: NADC=10;MADC=3;AOSR=128;R=2;P=1;J=1;D=28; *
* PLL_CLKIN =12Mhz *
* CODEC_CLKIN = PLL CLK=30720000 *
* CODEC_CLKIN = NADC * MADC * AOSR * ADCFS =10*3*128*8000 *
* PLL_CLK = PLL_CLKIN * R * J.D / P = 12000000*2*1.28/1=3072000 *
* PLL_CLKIN = MCLK = 12MHz *
* ADCFS = 8KHz *
* ------------------------------------------------------------------------ */

//1.Software Reset
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 1, 1 ); // Reset codec
USBSTK5515_wait_Test( 200 ); // Wait
AIC3204_rset( 0, 1 ); // Point to page 1
AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power

// 2.PLL and Clocks Dividers configuration and Power Up For 8KHz Sampling Rate
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 27, 0x0d ); // I2S interface, 16 Bit, BCLK and WCLK is set as o/p ,DOUT High Impedence
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 1 ); // PLL setting: J = 1
AIC3204_rset( 7, 0x00 ); // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0x1c ); // PLL setting: LO_BYTE(D)
//AIC3204_rset( 30, 0x88 ); // BCLK N Divider ->> DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, 0x12 ); // PLL setting: Power up PLL, P=1 and R=2
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 ->> Use with PRB_R1 to PRB_R6, ADC Filter Type A)
AIC3204_rset( 18, 0x8A ); // Power up NADC and set NADC value to 10
AIC3204_rset( 19, 0x83 ); // Power up MADC and set MADC value to 3

//3.Processing Blocks Configuration
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset(61,5); //Select PRB_R5

//4.ADC ROUTING and Power Up

AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset(10,0x43); //common mode control register
AIC3204_rset(51,0x68); //MicBias = LDO_IN
AIC3204_rset( 55, 0xc0 ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 57, 0xc0 ); // CM_1 (common mode) to RADC_M through 40 kohm
AIC3204_rset( 59, 0x5f ); // MIC_PGA_L unmute
AIC3204_rset( 60, 0x5f ); // MIC_PGA_R unmute
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC
AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC

AIC3204_rset( 0, 0x00 );

*/
USBSTK5515_wait_Test( 200 ); // Wait
prints("\rCodec Initialization done \n");
/* I2S settings */
I2S2_SRGR = 0x0015;
I2S2_ICMR = 0x0028; // Enable interrupts
I2S2_CR = 0x8012; // 16-bit word, Master, enable I2C
prints("\rI2S Initialization done\n");

Even the Configuration seems OK i am not able to take any valid input data from the codec,if i want to check the loop back how could i do for this configuration, Kindly please resolve my problem.

PCM9211 Clock Halt Issue

Atsushi Sasaki1 — Tue, 11 Jun 2013 00:50:45 GMT

Hello Sir,

I use PCM9211 with Digital Audio I/F and ADC function.

But I am in for trouble.

When SPDIF signal is halt (for example, pull out COAX cable), just a moment SCK/BCK/LRCKs halt.

[https://www.dropbox.com/s/0rqsk2r2z2qvkue/clipboard.jpg]

Ch1 is SCKO output(PIN20) and Ch3 is ERROR output(PIN 1).

So this behavior cause POP NOISE from DAC output!!

And this issue occur on PCM9211EVM.

(Please visit the site to view this file)

How can I avoid this issue?

Thanks.

Atsushi Sasaki

PCM3070 stereo fast limiter

Thomas Lake — Mon, 10 Jun 2013 18:00:02 GMT

I tried to used a DRC as a limiter (compression in region 2 = 25) and found it was way to slow to limit fast peaks in a voice or music signal. I'm now trying to use the stereo fast limiter component placed after the DRC. (LimitIn=0.75, ratio=0.5). It doesn't seem to work correctly. I would expect a sinewave input/output to become rounded or limited on it's peak as I get beyond the limit threshold but it doesn't occur on my oscilloscope. Is there any suggestions on how to implement this component?

Is there any other method to implement a fast limiter?

How fast is a stereo fast limiter component?

Regards,

Tom