Hello everyone ,
My project have configued the SAP CLOCK SLAVE MODE, and the MCLK, SCLK ,BCLK provided by the external clock source,
And the signal is right( 24.576M, 48k, 3.072M)
but after download the program created by PPS , the TAS3204init compent set to the slave mode, and the sine wave input from
the AIN, but now , the digital data signal is not out from the PIN SDO1(SDO2). and I change the program back to the master mode,
and then the digital data output from the SDO1(SDO2) !
who have the experence about this configuration? and provide me some advice!
I did some experiments, since I don't have the proper gedget to look at the signals at the pin, I was using PPS probe points. I found something similar. That whenever SFR 0xA2 is 0x00, the signal is gone, when I switch it to 0x40, I can see the signal.
One thing I also observe is that when it's slave mode, the input signal is gone from my side, can you check on your board whether that's the case as well?
I'll try to consult some HW people to see whether I can get some clue.
Yeah, In clock slave mode , input the SINEWAVE signal AIN PIN and the AOUT PIN there will be the output signal , then the DOUT have nothing out !
I think if In SAP CLOCK SLAVE MODE, the SAP will only receive the input digital signal, and for the SAP MASTER MODE will only send the digital signal output?
and the datasheet , EVM manual have been not clealy explained for the SLAVE MODE!
I notice one case in the EVM manual, its processflow include all the simulation signal route and the digital signal route ,
I have no EVM BOARD here,
you have one board? if you coulde run the example in the EVM BOARD and verify the result?
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