AES11 specifies an "output timing phase" requirement for AES3 signals:
5.3.1.1 - The difference between the timing-reference points of the digital audio synchronizing signal and all output signals, at the equipment connector points, shall be less than ± 5% (or ± 18 deg) of the AES3-frame period.
The AES term "frame" means "one LRCK cycle" in DIX4192 datasheet lingo.
As far as I understand, the DIX4192 DIT module has a clock input only, but no frame sync (LRCK) input. This means that the DIT is freely runing, without any determined framing relationship to neither the DIR, nor to any of the audio serial ports.
While looking for a solution, I've spotted the DIT module's BLS i/o and SYNC out pins (Fig. 11). What I need to end up with, is a SYNC signal with no more than ± 5% offset (with DIR input port as a reference). As far as I understand, BLS is for firing a new block preamble only, not for re-aligning the transmitter's SYNC frame.
What's the trick for tweaking the DIX4192 to adhere to the AES3/AES11 standards? - Thanks.
Wabri,
The DIX4192 does support AES data. For the serial audio ports, input data is then sent to an AES encoder before being sent out by the DIT. Likewise for the DIR, input data is sent to DIR buffers before being sent to DIT buffers (in accordance with AES standards) before being sent out. So no tweaks should be necessary to achieve AES output.
Patrick Galvin