Hi,
This is about the SRC4392, specifically, registers 0x32 and 0x33 (SRC Ratio Readback Register). The datasheet defines Register 32 as SRI[4:0] and SRF[10:8]. Register 33 is SRF[7:0].
In another post, someone asked and TI confirmed that it is simple to read. If the input rate is 48kHz and the output rate is 96kHz, then you should read 0.5.
In my application, I have the output rate set as 192kHz (by setting PortB as master, output data source = SRC, clock = MCLK, clock divider = 128). A 24.576MHz crystal oscillator feeds MCLK. I confirmed that this setting is correct by measuring a 192kHz clock at the LRCLK pin.
However, I am having a hard time understanding how to interpret registers 0x32 and 0x33. Here's what I get (remember output rate is 192kHz), values shown below are made by writing 0xB2 (register 0x32, auto increment enabled, read back 2 bytes).
44.1kHz = 01 D6
48kHz = 02 00
88.2kHz = 03 AC
96kHz = 04 00
For the 96kHz value for example, I'm expecting the Input-to-Output Sampling Ratio to be 96:192 = 1:2 = 0.5. SRI[4:0] = 0x00 so that is correct, but SRF[10:0] = 0x400 doesn't correspond with a "5". Since the readback values are increasing as the Input Sampling Rate goes up, it does appear to be working correctly.
Thank you.
