Hi,
From TAS1020B data manual, the USB sample rate clock (CSCLK) and master clock output (MCLKO) are tied with each other. Is there a way to separate them?
For example, for 32-bits stereo 48kHz audio data, CSCLK will be 32*2*48000 = 3.072MHz, and I also want MCLKO to be 19.2MHz or 9.6MHz, is it possible?
If the answer is yes, how to do it? If the answer is no, what is the alternative solution?
Thanks,
Alex
Alex,
> Is there a way to separate them?
No, as per Figure 2-1 in the data manual.
> Is it possible?
Since there's no small integer 'M' such that 19.2/M = 3.072, it's not possible synchronously. Could you use ACG1/CSCLK for the 3.072MHz output and ACG2/MCLK02 for the 19.2MHz output, since you apparently don't need the two signals to be synchronous?
Regards,
Frank
Frank,
Can you elaborate on the part of "using ACG1/CSCLK for the 3.072MHz output and ACG2/MCLK02 for the 19.2MHz output"? Yes, I don't need the two signals to be synchronous, but isn't only one can be used for I2S streaming data? How to use both ACG1 and ACG2 for the same I2S streaming?
In all cases I've seen, the MCLK to the codec has to be some multiple of Fs, and in particular, MCLK has to be an integer multiple of BCLK. For 48kHz, the BCLK is 3.072MHz as you indicate, and MCLK is typically 8 x BCLK, or 24.576MHz. The codecs that I've seen seem to do OK with this.
You indicate that you need to produce something like 19.2MHz or 9.6MHz or something similar - so your codec must not need MCLK and BCLK to be related like I've seen (i.e., by a frequency divider). I don't understand what you're saying, but I assume that you know what you're doing.
You can let the ACG1 produce MCLK at 24.576MHz, dividing down to a BCLK of 3.072MHz - but you don't have to use that MCLK at your codec. You can use ACG2 to develop a different MCLK02 that is 19.2MHz or 9.6MHz.
Perhaps you could share your intent as to the I2S codec you intend to use - maybe that would help clarify your purpose.
The I2S codec has only one requirement: the MCLK is 19.2MHz or 9.6MHz.
The other requirement is for CSCLK to be either 3.072MHz or 1.536MHz.
How to exactly set up the ACGs to get the above setup? From the data manual, it says if using ACG2, then both CSCLK and codec MCLK will be sourced from ACG2?
Please see the TAS1020B Data Manual http://www.ti.com/lit/ds/symlink/tas1020b.pdf.
In particular, see Figure 2-1. Setup Frequency Synthesizer 1 to develop your 3.072MHz CSCLK, and Frequency Synthesizer 2 to develop your 19.2MHz MCLKO2. Don't connect MCLKO to your codec - use MCLKO2 instead.
If using synthesizer 1 for CSCLK and synthesizer 2 for MCLKO2, and connect MCLKO2 to codec clock, will it require asynchronous streaming? The USB device descriptor needs to be modified for asynchronous transfer? How about SoftPll(), is there any change required for this kind of usage?
The TAS1020B doesn't know that your codec isn't using MCLKO, so the switch from using MCLKO to MCLKO2 is invisible to it.
This assumes that you're correct that your codec can use a master clock that is not related to the bitclock and wordclock, and responds appropriately to the bitclock and wordclock that the TAS1020B provides.
So I don't think that change necessitates using asynchronous synchronization.
Tried your suggestion, and it is promising. The headphone mode partially works with MCLKO set to 24.576MHz and MCLKO2 set to 19.2MHz, but there is some sync issue with MCLKO2. In function SoftPll(), it uses ACGCAPL and ACGCAPH to sync SOF with MCLKO (least 16 bits). Is there a similar register such as ACG2CAPL and ACG2CAPH for MCLKO2? Checking with Figure 2-1 of tas1020b.pdf, it shows that only MCLKO line has a 16-bit counter for SOF.
I tried to use the same ACGCAPL and ACGCAPH to sync MCLKO2 with SOF in function SoftPll(), but it did not work. Here is what I did:
Change SOF_EXPECTED_DELTA from 24576 to 19200, and use the MCLKO2 frequency value 0x7D0000 instead of 0x61A800.
I am going to try one thing here: use the same ACGCAPL and ACGCAPH to sync SOF with MCLKO2, but with the same ratio as MCLKO2/MCLKO (19.2MHz/24.576MHz). Hope this will solve the issue above.
Why are you adjusting ACG2 based on SOF?
The only reason to adjust ACG2 would be to try to obtain an output which was 'synchronized' with the host's (SOF) clock - but I've understood from what you've said previously that that's not a requirement.
Frank Minich The only reason to adjust ACG2 would be to try to obtain an output which was 'synchronized' with the host's (SOF) clock
The only reason to adjust ACG2 would be to try to obtain an output which was 'synchronized' with the host's (SOF) clock
What if I do need to adjust ACG2 to support the audio streaming between PC and TAS1020B and my codec? Is there a way to do it correctly? The ratio-sync of ACG2 based on ACGCAPL and ACGCAPH did not work.
What do you need MCLKO2 to be, relative to anything?
Most TAS1020B users who want to use synchronous isochronous transfers adjust the ACG settings via softPll() to 'close the loop' - but that's immaterial if you don't need your codec's master clock to be somehow related to BCLK and WCLK.
My codec's master clock needs to be on 19.2MHz, but my codec is processing the same audio stream data coming from/going to PC via TAS1020B. In that case, shouldn't it be adjusted for PC host clock (SOF)?
Looks like the only way it might work for my case is to use asynchronous transfer? How does async streaming work with TAS1020B?
BTW, there might be a bug in file "SoftPll.c" function "softPllInit()": the first statement
EngFrq = 0xA800;
ACG frequency is 0x61A800. Since it only adjusts the 16 MSB of the fraction (total 18 bits), shouldn't it be like below?
EngFrq = 0x6A00;
It is only the initial value, so I don't think this will change much for my case. Just want to point out a potential bug in the code.