I am not sure about the approach on sampling my digitized audio from an external source. My current setup consists of an MCLK clock of 24.576MHz which is also tied to the BCLK. With this clock speed, I can achieve super high quality audio but I only need 8bit 8kHz quality audio.
I've already posted another message on this and nobody answered although my post got 31 views. Can someone please help?
On my EVM board, I physically tied a piece of wire between my DOUT and my DIN pins to ensure that what was coming-in on my input IN1 (J1) was going out on my output (J9). That all works fine. I can also see my data with my scop on the DOUT (to DIN) pin.
I can read/write all registers on the AIC3204 through a command-line interface tied to a PIC over RS232.
So, I figured that if I have to read each bit of data on each BCLK tick, 24.576MHz is way too fast for my PIC running a 16.384MHz clock therefore I figured that I could perhaps lower the BCLK speed to 512kHz using a PWM on my PIC.
If I was to provide MCLK and BCLK a 50% duty cycle square wave from a PWM at 512kHz, how would I be able to achieve 8bit 8kHz audio? Do I need to use the PLL rather than simple MCLK for the CODEC_CLKIN?
I am just not sure what approach to take to be able to sample the data on the DOUT pin. I can use the WCLK to get the left-right audio, the BCLK to clock-in the bits, but I need someone to help please.
In order to get a proper and fast response we need the correct part number as the subject. If part numbers do not match, our ombudsman has to go through all the queries and forward to the right people. The part number mentioned here AIC2304 which we do not have presently. I am assuming you are looking for AIC3204, mentioned else where in the query
What is the data format you want to use, is it I2S or DSP? Is it recording or playback or both? AIC3204 can be configured for 16bit, 20bit and 24bits and since you want to get 8bit data only, depending on the format the controller has to do additional processing. Assuming AIC3204 is configured as slave,
Since you have a master clock that has interger relationship with respect to WCLK frequency and is within the dividers range, you do not need to turn on the internal PLL.
For playback configure the device as follows:
Fs <-- DOSR <-- MDAC <-- NDAC <-- CODEC_CLKIN
8KHz * 768 * 2 * 2 = 24.567MHz
Fs <-- AOSR <-- MADC <-- NADC <-- CODEC_CLKIN (Note: see below)
8KHz * 256 * 6 * 2 = 24.576MHz
Now for achieving the 8bit data @ Fs 8KHz with 512KHz bit clock
In I2S mode, after the falling edge of WCLK device will start sending the left channel data for 16 clocks and wait till it sees a rising edge of WCLK before it sends right channel 16bits. The data is MSB first and processor can ignore last 8 LSB bits for both channels. If the Fs clock frequency is reduced to 128KHz with 50% duty cycle, the device can only send 8bits of left and 8bits of right. This way processor does not require to do additional processing.
In DSP mode, (refer the timing and edges in the datasheet) the device will send the 16bit left immediately followed by 16bit right. Here it will need 32 bclks for one Framesync and the data processing has to be done by the processor.
Note: Corrected the typo in the interest of people referring the forum
Thanks for your reply. You are correct, it is 3204 not 2304 - that was a typo.
Not sure about the format I want to use, I guess I2S would be the simplest? And I eventually want to be able to do both but I believe that before I am able to do either of them, I must understand what I'm up against which is why I posted my message.
So based on your reply, I have two choices:
1) If I use a 512kHz bit clock, I can sample the first 8 bits of the 16 bit sample but then I'll have some overhead to compensate for the extra 8 bits I don't need.
2) If I use a 128kHz bit clock, then I will only be receiving 8 bits of data.
Is this correct?
This leads me to two other questions:
1) If I want to do 11.025 kHz sampling, what type of clock would I use and what would be the impact on the data bits?
2) I'm still trying to digest all this clocking mechanism so bear with me please. Let's say I use 128kHz BCLK signal to avoid the extra bit overhead, do I still need to provide my external MCLK pin with my initial 24.576MHz signal? I'm still a bit confused here on the correlation between the BCLK and the MCLK... In other words, will I still be able to achieve 8bit 8 kHz audio if I give the BCLK pin a 128kHz clock while also lowering the MCLK signal?
Acutally, I guess the other question I should also ask is let's say that I keep the MCLK at 24.576Mhz and that I now have the BCLK pin as 128kHz (set it up while typing this message), how would I configure the NDAC / MDAC / NADC / MADC / DOSR and AOSR parameters?
As mentioned in earlier posts, it is difficult for me to directly try different options as my USB board is defective and the only way I can talk to my CODEC is through my console application and manually configuring the registers through the options provided to me by my circuit. I can read / write any register but I just need to know which ones in order for me to achieve my goal.
I think I got it to work with the settings you gave me but I believe you have some typos in your response below:
Fs <-- AOSR <-- MDAC <-- NDAC <-- CODEC_CLKIN
In both cases above, you specified MDAC and NDAC but in the second part, it should have been MADC and NADC.
I think I'm starting to understand. So, in the AIC3204 application, although the USB board is dead, under the DIGITAL SETTINGS > CLOCKS / INTERFACE > DIVIDERS tab, if I plug-in the values you gave me, it results in the following:
DAC_CLK: 12288kHz, DAC_MOD_CLK: 6144kHz and DAC_FS: 8kHz
ADC_CLK: 12288, ADC_MOD_CLK: 2048, ADC_FS: 8kHz
Why are the DAC_MOD_CLK and ADC_MOD_CLK different?
So at the moment, I still have my 24.576MHz clock in the MCLK pin but I have a 128kHz PWM 50% duty to the BCLK pin. And it results in what seems to be 8k 8 bit audio. The only thing I am noticing is that there's a random CLICK in the audio. And if you don't mind, although it is working, I'd still like clarifications to my previous post with questions. Thanks so much!
Glad to know that things are working for you. About the ADC clock path, the dividers must be MADC and NADC as you have mentioned.
If you want to do 11.025KHz sampling with 24.576MHz clock, you will need to turn ON the internal PLL, because of non integer relationship between them and fractional multiplication is possible in PLL.
DAC Sampling @11.025KHz
Fs <-- DOSR <-- MDAC <-- NDAC <-- PLL<--MCLK
(11.025KHz * 512 * 2 * 8 ) / 3.6750 = 24.576MHz , here 3.675 is the PLL multiplication, J=3, R=1, D = 6750
You can change the MCLK frequency that have a integer relationship with the clock tree.
Please read through the D/S sections for the PLL about the frequency ranges. Note the change in the DOSR value here (refer the D/S for DAC modulator max frequency information, DAC engines etc) . Similarly you can do ADC configuration. The PLL out is common for both ADC and DAC engines.
The BCLK is independent of the above frequencies except when the device is operating as master.
With BCLK frequency of 128KHz, you can go do only 8KSPS sampling. (8bits+8bits)*8KSPS = 128KHz.
You will have pump up the BCLK for using 11.025KHz
Ok, got it for the PLL part. Yes, it would make sense to use the PLL if I want to achieve sampling rates that aren't multiples of the frequency.
Now it's just a matter of understanding the clocking. I've read through the 3204 datasheet multiple times but I'm still confused.
So, if I use the AIC3204 software (just as a visual interface for the calculations but I'll manually enter the values afterwards through my own console interface) under the DIGITAL SETTINGS > CLOCKS / INTERFACE > DIVIDERS TAB, I put-in the values you suggested:
NDAC: 2, MDAC: 2, DOSR: 768
NADC: 2, MADC: 6, AOSR: 256
These values give the following result on the right-hand side:
DAC_CLK: 12288 kHz, DAC_MOD_CLK: 6144 kHz, DAC_FS: 8 kHz
ADC_CLK: 12288 kHz, ADC_MOD_CLK: 2048 kHz, DAC_FS: 8 kHz
In both cases, I end-up with 8 kHz sampling, which is really what I want. But, there are other combinations that ALSO result in 8 kHz such as if I set AOSR to 128 and set MADC to 12. This calculation however changes ADC_MOD_CLK to 1024. Why wouldn't I use these values instead of the ones you suggested? If I do the calculations, it still arrives to 24.576MHz:
You: 8000 Hz * [AOSR 256] * [MADC 6] * [NADC 2] = 24 576 000 Hz
Me: 8000 Hz * [AOSR 128] * [MADC 12] * [NADC 2] = 24 576 000 Hz
So as much as I've read through the datasheets multiple times, it's still not clear to me - what should I consider when choosing these values? And what's the purpose of the DAC_MOD_CLK and ADC_MOD_CLK? And the DAC_CLK / ADC_CLK? What criterias / logic must I follow in order to choose the proper values? In the case of the A to D, with your calculations, the ADC_MOD_CLK is 2048 Hz. With my calculations, the ADC_MOD_CLK is 1024. But the end result is still 8 kHz sampling.
I'm trying to understand the relashionship between all these values.
Another question: why do I get the same audible audio quality if I provide the BCLK with either a 128kHz 50% duty signal or just feed it with 24.576MHz signal? The only audible difference I can hear is when I feed the 128kHz signal to BCLK, that's when I hear some random clicks mentioned in a previous post. If I swap the 128kHz with the MCLK of 24.576MHz, then the clicks are gone but the audio quality remains unchanged. Why?
You are free to choose any of the clock settings the tool is giving, under one condition is that the clock tree meets all the frequency requirements. It is explained in the DAC setup section of the D/S. (My answers here are referenced to the DAC block and same applies to ADC). The faster the clock higher up in the clock tree will burn more power, so it is better to set the divider in such a way that the frequency is just sufficient at the DAC Engine level. The MDAC, NDAC and DOSR numbers can be optimized depending on the performance requirement and the PRB modes you would like to use.
Refer to the Application note here http://www.ti.com/lit/an/slaa404c/slaa404c.pdf
Also refer the application notes listed under this device.
So, basically, the "guideline" to follow is regardless of the values used for the MDAC, NDAC, MADC, NADC, DOSR and AOSR fields, as long as their calculations work-out for the selected MCLK frequency, then it's just a matter of choosing the right values to have the lowest possible xxC_CLK and xxC_MOD_CLK frequencies to ensure the least amount of power is consumed?
Because like I said in my last post, with your suggestion of values:
I get this result:
And changing your values to mine, I get this result:
ADC_CLK: 12288 kHz, ADC_MOD_CLK: 1024 kHz, DAC_FS: 8 kHz
The outcome for both is that I get 8kHz sampling with a base MCLK frequency of 24.576MHz but it's just at the divider level that the changes are made. The only difference is that in my case, since MADC is set to 12 ans AOSR is set to 128, it'll consume more power than your setting because your MDAC is 6 and your AOSR is 256?
And what about the question concerning the audio click? As I stated:
Why do I get the same audible audio quality if I provide the BCLK with either a 128kHz 50% duty signal or just feed it with 24.576MHz signal? The only audible difference I can hear is when I feed the 128kHz signal to BCLK, I hear some random clicks and pops but if I swap the 128kHz with 24.576MHz, then the clicks and pops are gone. What can cause this?
You are right, it is speed vs power vs performance. The device offers power tuning flexibility for the performance that is required.
Regarding the occasional clicks, can you confirm that the clock edges is as per the data protocol that you are using. Also can you check if the data is exactly same when you are using higher BCLK vs 128KHz clock.
We have not tested the device in the configuration that you are not using, as it is not native to the device. The device will always use the 16bit internally, but using the slower bit clock you have provided MSB 8bit and do not know what is the LSB 8bit. This could create DAC output to jump depending on LSB bit values. When you are feeding the higher bit clock, the device gets full 16 bit data (may be you are padding the 8 LSB bit with 0).
Ok, I will test the clicks with higher (512kHz) BCLK and see if it still occurs since as per your explanation, only 128kHz will provide 8 bits of output otherwise, I'll get the full 16 bits. I'll test and let you know.
You'vre provided the above answer a long time ago but I currently am looking at making my sampling frequency to be 11.025kHz and your calculation does not work. You indicate that J=3 but the minimum for J is 4.
I made myself a spreadsheet where I plug-in any values and the calculations are adjusted for each field. All my calculations work with the values I see in the AIC3204 application. However, using a 24.576MHz base clock as the input of the PLL, I just cannot find the right values to obtain an ADC_FS of 11025Hz.
So at the moment using an MCLK of 24.576MHz and a BCLK of 128kHz 50% duty, I have perfect 8K-8bit mono.
In my code, I have the ability to change the BCLK whatever I need up to about 2.048MHz @ 50% duty. The MCLK of 24.576MHz frequency is fixed and can either be programmed as MCLK or input to PLL (PLL_CLKIN).
What I have and what I am looking for is to have sampling frequencies of 8kHz, 11.025kHz and 22.5 kHz, each in 8 and 16 bit samples while maintaining my 24.576MHz clock.
You had told me in the past that using a 128kHz BLCK I would no have more than 8-bit samples which is perfect as the CODEC returns me an 16kHz WCLK (left channel high, right channel low).
So now, in order to get 11025Hz and 22050Hz ADC_FS clocks, how in the world do I calculate given that my MCLK is 24.576MHz and that I will require a PLL? And what speed of BCLK will I need to provide? And how many bits will each sample be?
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