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Systemclock for PCM3002 Audio Codec
first of all, i'm sorry for my bad english,...
I have the following problem:
I'm using the DSP TMS320C6418 and want to connect the PCM3002 Audio Codec with the McBSP of the DSP.
But I can not find any description, what Systemclock should be used for the Audio Codec.
In future, it would be fine to change the sampling rate of the audio codec by software, but what systemclock and bitclock should be used?
The only thing to system clock writen is in the datasheet: "systemclock and bitclock must be synchronised..."
What is the best way to connect the Audio Codec to the DSP?
Thanks for your help!
Sys Clock requirements can be found in Table 1 on Page 22 of the PCM3002 data sheet. LRCLK will be at the sample rate and BCLK needs to be at least = Fs * Number of bits * 2.
This is a good primer on connecting the McBSP to an audio bus: http://focus.ti.com/lit/an/spra595/spra595.pdf
This may help as well...general clock divider for PCM3002
It is not the strongest of the species that survives, nor the most intelligent that survives. It is the one that is the most adaptable to change. - Charles Darwin
First of all: thanks for your help!
but, we have also one problem: because of the reason, that we can not provide the clocks with the DSP we want to provide to the PCM3002,
we want to use a programmable clock synthesizer (CDCE906).
but which clock input can i use from the dsp ? the problem is that i am not able to produce for example 12,288MHz and 48kHz with the clock synthesizer, so that I have to divide the 12,288MHz to 48kHz with the DSP. But in the McBSP Ref. Guide is written, that i only can divide by 32....
Do I have to change the connection to the McASP ? May this be a better solution?
As System Clock for the DSP, we will use a 30MHz Quarz.
Questions about questions...
at least: sorry for my bad english,...
I work with DSPs, so I may not understand about the other components you are taking about and I’m not sure if I understand the question…
A lot of information about what you need is at the datasheet of the C6418 page 75 to 78:
By “System Clock for the DSP” I assume that you mean (let me know if I’m wrong) that you mean the crystal that you are going to use as input to the PLL. This input can be multiplied by the PLL MULTIPLY FACTORS to generate a CPU clock up to 600 MHz (or 500 MHz depending on what part number you are using).
The internal clock that goes to the McBSP would be CPU/4, which for CPU = 600 MHz would be 150 MHz.
Looking at the McBSP user’s guide:
Looking at the diagram on page 18, you can use an internal source clock, that for C6418 will be CPU/4 clock and divide. On page 74, the clock divider (CLKGDV) can be up to 255 (FF).
So 150 MHz/(255 + 1) ~= 585 KHz, that from what I understood is too fast for you as you want 48KHz for the McBSP clock.
So instead of using an internal clock source (see figure 6 page 18 of the McBSP user’s guide), you could an external clock source (CLKS) and divide it up to 256.
I’m not sure if that was what you where asking, let me know.
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thanks for your answer, yes it helps!!
now just to be shure:
I want to connect an audio codec like the PCM3002 to the DSP, but the main problem is, that the audio codec needs synchronous clocks( Systemclock, Sample rate clock, bitclock), which are very sensitive.
To solve this problem, I want to use an external clock generator,...
The connection of the audio codec via I2S is described in http://focus.ti.com/lit/an/spra595/spra595.pdf
on page 4 figure 2. DSP(transmitter/receiver) as Master and the audio codec as Slave (transmitter/receiver).
The clock generator gives a main clock to the DSP on pin CLKS, and the Systemclock to the audio codec.
The audio codec is connected to the following DSP Ports: CLKX (bitclock, between 1,2MHz and 1,92MHz), FSX(sample rate clock, between 30kHz and 48kHz) , DR(data receive) ,DX(data transmit).
Does this configuration work?
Sorry for confusing bit clock with sample rate at me previous post, so you can have FSX as sample rate clock at 48 KHz because you can divide the clock bit (FPER).
If the clock generator is going to CLKS for the DSP and the System Clock for the codec, you have to be careful because there will be a delay between CLKS and CLKX, FSX,DR, DX... Please see page 131 of the datasheet for the delays.
So there is going to be a delay between the signals that are coming out of the DSP and the System Clock (as it comes directly from the clock generator and it does not pass in the DSP). Please take a look at the delays and see if it is going to be a problem...
the delay will be a constant delay, so that i will have a constand phase displacement that is not a problem for the audio codec as you can see on page 24 of the datasheet: http://focus.ti.com/lit/ds/symlink/pcm3002.pdf
ok, thanks for your help!
now i am going to do the layout for the printed curcuit board....
while routing the PCB design, we are having problems with other devices....
now we are in discussion if it would be possible to simply change the connection for the audio codec:
it was planned to connect the Audio Codec PCM3002 to the McBSP via I²S like described in
but now, the question is:
is it possible to simply connect the audio codec to the McASP ?
thanks for your help!
I think i should be a litte bit more precise...
is it possible to connect the system clock input with the AHCLKX output from the McASP?
the System Clock input requires a clock of 12,288MHz....
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