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Adaptive Filtering Function of TLV320AIC3206 Audio Codec

Jeffrey
Expert 1920 points
Other Parts Discussed in Thread: TLV320AIC3206

Dear all.

I want to know the operation of adaptive filtering in TLV320AIC3206 EVM.

The bypass mode (Input : Line in or Mic in -> Output : Headphone) is normally operated in EVM.

But if the adaptive filtering is enabled, the bypass mode is not operated

and the USB playback mode is only operated.

So, I want to know that it can be used as follow concept or routing.

Input (Line in or Mic in) -> Adaptive Filtering -> Output (Headphone)

I'm looking forward for your reply.

Thanks...

  • 0
    TI__Guru 51346 points

    You'll have to route the stereo ADC output to the stereo DAC input for this to work. (Page 0, Register 29, bit D4).

  • 0 in reply to Dominik Hartl11
    Expert 1920 points

    Dear D.Hartl

    Thank you for your information.

    EVM operation is good, but my customer board is not normally operated.

    I want to know the change point.

    Refer to follow attachments.

    0552.Simplified Diagram.pptx

    7317.Input MIC(IN3)_ADC to DAC enable_v0.4.txt 
    //Soft Reset
w 30 00 00
w 30 01 01 (Soft Reset to initialize all registers)

w 30 00 00
//PLL Clock
w 30 04 03 (Clock Setting 1, PLL Clock=CODEC_CLKIN)
w 30 05 D1 (Clock Setting 2, P=5 and R=1)
w 30 06 24 (Clock Setting 3, J=36)
//ADC Clock
w 30 12 83 (Clock Setting 8, NADC=3)
w 30 13 85 (Clock Setting 9, MADC=5)
w 30 14 78 (ADC OSR)
//DAC Clock
w 30 0B 83 (Clock Setting 6, NDAC=3)
w 30 0C 85 (Clock Setting 7, MDAC=5)
w 30 0D 00 (DAC OSR, MSB)
w 30 0E 78 (DAC OSR, LSB)
//Audio Interface
w 30 1B 0C (Audio Interface 1, BCLK/WCLK Output)
w 30 1E 85 (BCLK N Divider=5)

//Adaptive Filter Coefficient
w 30 00 2C
w 30 0C 00 00 00 00 0A BE 8D 00 00 00 00 00 00 00 00 00 00 00 00 00
w 30 00 2D
w 30 14 00 00 00 00 0A BE 8D 00 00 00 00 00 00 00 00 00 00 00 00 00
w 30 00 3E
w 30 0C 00 00 00 00 0A BE 8D 00 00 00 00 00 00 00 00 00 00 00 00 00
w 30 00 3F
w 30 14 00 00 00 00 0A BE 8D 00 00 00 00 00 00 00 00 00 00 00 00 00

//Power Configuration
w 30 00 01
w 30 01 08 (Disabled connection of AVDD with DVDD)
w 30 02 00 (Master Analog Power Control)
w 30 47 32 (MicPGA Startup Delay to 3.1ms)
w 30 7B 01 (Reference Charging time to 40ms)

//Input Routing
w 30 00 01
w 30 33 50 (Mic Bias Config, 1.4~1.7V)
w 30 34 04 (Left MicPGA Positive Input Routing)
w 30 36 40 or 41 (Left MicPGA Negative Input Routing)
w 30 37 04 (Right MicPGA Positive Input Routing)
w 30 39 40 or 41 (Right MicPGA Negative Input Routing)
w 30 3A F0 (Floating Input Config)
w 30 3B 00 (Left MicPGA Volume Control)
w 30 3C 00 (Right MicPGA Volume Control)

w 30 00 00
//ADC Setup
w 30 51 C0 (ADC Channel Setup ? L/R ADC Power Up)
w 30 52 00 (ADC Fine Gain ? L/R ADC Channel Unmute)
//ADC Adaptive Filter
w 30 00 08
w 30 01 04 (ADC Adaptive Filter Enable)
//ADC to DAC
w 30 1D 10 (ADC Output to DAC Input)
//DAC Setup
w 30 3F D4 (DAC Channel Setup - L/R DAC Power Up, Routing)
w 30 40 00 (DAC Channel Setup - L/R DAC Channel Unmute)
//DAC Adaptive Filter
w 30 00 2C
w 30 01 04 (DAC Adaptive Filter Enable)

w 30 00 01
//Output Routing
w 30 0C 08 (HPL Routing Selection)
w 30 0D 08 (HPR Routing Selection)
w 30 09 30 (Output Driver Power Up)
w 30 10 00 (HPL Driver Gain - Unmute, Gain 0dB)
w 30 11 00 (HPR Driver Gain - Unmute, Gain 0dB)

    I wish that you reply to my request as soon as possible.

    Thanks...