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TLV320DAC23 - clock question

Percy Shadwell
Prodigy 80 points

If I am feeding in data at 8K SPS and the Sample Rate Control (Address: 0001000) is set for Normal mode at 256Fs, it seems that MCLK should be 2.048MHz .  I do not see how to resolve the SRx bits in that regiater for an MCLK this low.

Can you help me?

What if I made the TI chip the master on the DCI port?  MCLK = ?

  • 0
    TI__Mastermind 28585 points

    Hi Percy,

    The sample rate scales exactly with MCLK so you can pick any values off the chart where Fs = MCLK/256.

    You can use the defaults with MCLK at 2.048 MHz. Putting the codec in master mode is usually your best bet as this avoids any chance of getting MCLK and LRCK out of sync.

    Best Regards,

    dave