SRC4392 Requirements for MCLK and RXCKI

Hi Kato-san,

I will look into this and get back to you when I can confirm information.

Justin

Hi Justin-san,

Thank you for your reply.
I am looking forward to hearing from you.

Best Regards,
Kato

Hi Kato-san,

Your understanding that the clock signal will be extracted by the DIR part from the AES3 signal is correct, this is detailed on page 24 of the SRC4392 data sheet. As for the clock specifications such as jitter tolerance for RXCKI, we do not have data for this characteristic.

Other clocking information can be found in the Electrical characteristics tables starting on page 4 (MCLK) and page 6 (RXCKI) of the data sheet.

MCLK: MIN: 1 MHz MAX: 27.7 MHz

RXCKI:  MIN: 3.5 MHz MAX: 27.7 MHz

Justin

Hi Justin-san,

Thank you for your response.
Is my understanding correct although I believe that it is possible to use a similar part as the clock source if the specifications of the cmos oscillator which are mentioned in the user's guide of SRC4392 evm are met?
Could you please give me your advice?

Best Regards,
Kato

Hi Kato-san,

From the datasheet on page 24:

"It is recommended that the clock sources for MCLK and RXCKI input be generated by low-jitter crystal oscillators
for optimal performance. In general, phase-locked loop (PLL) clock synthesizers should be avoided, unless they
are designed and/or specified for low clock jitter."

Justin

Hi Justin-san,

Thank you for your reply.
I asked you about that since I had already found and read this description which is mentioned on page 24 of SRC4392 data sheet.
Do you have any additional required specifications in detail?

Best Regards,
Kato

Hi Justin-san,

Thank you for your reply.
I understood, will inform our customer of this information.

Best Regards,
Kato