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Output range on PCM1753

Other Parts Discussed in Thread: PCM1753

I am using a PCM1753 to output control voltages to an instrument - one voltage is DC, the other is 10KHz, and I notice that the filtered output covers only about half the full-scale range (I am still in DC test mode).

The unfiltered output clearly shows a large artifact that is minimal at mid-range, then increases in the positive direction when a positive output is driven, and in the negative direction when the output goes negative. The artifact is about 1 volt in amplitude and is at the sampling frequency.

The range of output is limited by the maximum excursion of this artifact - at full scale data it reaches the maximum level of 2 volts peak, but the filtered voltage never gets higher than about 1 volt less.

The system clock is 12.5MHz and the frame rate is 130.208 KHz (6.25 MHz data clock and 48 bits per frame). We have tried it at twice these frequencies and at 64 data bits per frame (shifting data as 32 bit right justified - at the  lsb - and padding the high order 8 bits) Nothing seems to change this behavior. Is it necessary that the system clock be an exact multiple (128 or 192) of the frame rate for the digital filter to operate properly? The response curves do not seem to indicate this.

  • Hi, Lee,

    I'm not sure I follow. Can you post some scope shots of what you're seeing?

    -d2

  • Here are three PicoScope traces of the analog output direct from the chip. The data is a binary countup cycling from max. positive to max. negative. Frame period is 5.21usec.

    What seems to be varying is the p-p voltage of the ripple. We have filtered this output (the last waveform) and this produces a DC output ranging from 1.356V to 3.729V

    Since filtering in the PCM1753 is digital based upon the high-frequency clock we should specify that this clock is 12.5Mhz, and the bit clock is 6.25 MHz.

    Please let me know if I am doing anything wrong here. We will try to continue with the filtered output appropriately scaled, but would like to hear your informed opinion on this matter. 

    4812.PCM1753_AnalogCountUpPerformance.docx

  • Our software enginers have determined that the ratio of SCLK to BCLK must be 4:1, not 2:1 as we had it previously - for our 48-bit sample cycle this amounts to 192 x fs. The artifacts disappear (or are drastically reduced) when this 4:1 ratio is implemented.

    I am therefore terminating this inquiry.

    Lee Felsenstein