PCM512x datasheet update

Hello Diego,

It's a work in progress. We're releasing the PCM5242 (a differential output version of the PCM5142) very soon. All datasheet efforts are going into that device. It shares much of the clock tree and other configuration registers with the PCM512x and PCM514x family. One that device releases to market, we'll start re-using the material for the update of the PCM51xx family.

Thanks again

Dafydd Roche

Hi Dafydd,

Thanks for the information, but I must say that I find this delay terribly long (the update was about to be released a year and a half ago!). What is the expected date for release of the PCM5242 datasheet and the update to the PCM512x datasheet?

For the moment I can support up to 48 kHz audio in our system using the charge pump clock output via GPIO3, which is documented in the current PCM512x datasheet. But for higher frequencies I would need to use the currently undocumented features to output a faster clock derived from the PLL output.

Hi again,

I am having a bit of trouble with this setup. I managed to output a clock from GPIO3 by using the charge pump clock which is 32*Fs, the intent being to use it as an audio master clock at the audio source (a McASP). While testing this I still had a BCK and LRCK that were derived from another clock (but had only an approximate rate) and running.

Now I have switched the McASP's master clock to the PCM5121's charge pump clock output on GPIO3, so the BCK and LRCK depend on the charge pump clock being active, but there is no clock signal on this output any longer.

My guess is that since BCK and LRCK are not present (because they depend on the clock output from the PCM5121) the charge pump is disabled and hence there is no charge pump clock to output. I tried disabling all clock detection on register 0x25 (setting it to 0x7E) and still there is no output clock. The PLL reports as locked, so the PLL appears to be running.

How can I either force the charge pump clock to be active or output another clock on GPIO3? The clock rate needs to be an integer multiple of 32*Fs, the lowest the better for EMI.

Thanks,

Diego

Hi there,

Is there anyone from TI who can help to get the PLL clock out of the codec on GPIO3 as requested above?

Thanks in advance,

Diego

Hi,

Sorry for taking some time to respond.

Thanks for this info but I think it is not of much help in our case.

In our application we do not need the PCM to be audio master in the traditional sense, that is we do not need it to generate BCK and LRCK, so I do not think that I would need to loop back a GPIO output to SCK.

What we want is for the PLL to generate the audio master high frequency clock (any multiple of 32*Fs) and output it on a GPIO. This high frequency clock would then go as input to the AHCLKX pin of a McASP and the McASP would divide it down to generate BCK and LRCK.

In our current design we cannot loop back a GPIO to SCK and furthermore the non-audio clock is tied to SCK, but we have a GPIO connected to the AHCLKX pin of the McASP. So I would need the information as to how to configure the PCM5121 to output the PLL clock on a GPIO. Unfortunately that bit of information is missing in the datasheet although an upcoming datasheet update containing the info was announced more than a year ago.

I see also that the PCM5242 that's has been talked about still has a datasheet preview only, containing almost no information. From where does the above figure come from? Maybe that datasheet contains sufficient info about the necessary register settings?

Thanks,

Diego