• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 29 subscribers
  • Views 281 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCM5121 Internal PLL Mode

William Slattery
Prodigy 60 points
Other Parts Discussed in Thread: PCM5121

Hi,

We are designing in the PCM5121 DAC into a product that requires the audio sample clock to be locked to a video timebase and we are hoping to do this without the expense of a dedicated synthesizer for the audio clock.

The video reference clock is 148.5MHz and we are considering using a numerically controlled oscillator inside an FPGA to generate the DAC SCK and run the DAC in master mode and then use its BCK and LRCK to clock data into the DAC.

Using this approach the digitally generated SCK would be exactly frequency locked over time but individual SCK clock periods may vary. For example, if SCK is nominally 12.288MHz and is digitally generated using our 148.5MHz video clock then most SCK periods would be 12 of the 148.5MHz clock periods (12.375MHz) and every few clocks the SCK period would be 13 of the 148.5MHz periods (11.42MHz) in order to keep the average at 12.288MHz. Over time the synthesized SCK frequency would be exactly 12.288MHz.

We are using the part in VREF mode with a sampling frequency of 48KHz.

Questions:

1) Will the internal PLL operate with a digitally generated SCK as described? And will it then generate a 'clean' monotonic BCK?

2) If so, what would the preferable SCK frequency be? In the mode we are using it, the PCM5121 accepts an SCK in the range of 1.536MHz to 49.152MHz. If we used a slower clock there would be less variation in the digitally generated SCK periods. Would there be any advantage one way or the other?

Appreciate your advice.

Regards

Bill Slattery

ImmediaTV Corporation

  • 0
    TI__Mastermind 28585 points

    HI Bill,

    1) Yes, this should work. I wouldn't worry too much about BCLK since this just clocks bits into the buffer. The bigger concern is LRCK since any jitter here could degrade SNR and THD. You would really need to try it to verify that you are getting the performance you need since we have no way to simulate or test your exact clocking.

    2) In general, you want to use the fastest clock (12.288 or 24.576 MHz) with the lowest jitter you have available. Ultimately you have to test it and look at SRN and THD to see if you are getting the performance you need.  

  • 0 in reply to Converter Apps
    Prodigy 60 points

    Thanks for the quick response.

    I'm not sure what the concern is with LRCK. The way I read the data sheet is the PLL clock drives the DSP and the DAC itself and that LRCLK is just used to frame the samples.

    In any case, after looking more closely at the data sheet I see it is possible to run the chip is slave mode and drive the PLL directly off of BCK (not using SCK at all). This way I could drive BCK, LRCK, and DIN and would be even simpler.

    So in my 48KHz sample rate case BCK is at 3.072MHz. If BCK at this rate was digitally synthesized from the 148.5MHz clock do you expect the internal PLL clock provided to the DSP clock would be 'clean'? Obviously my concern with this arrangement is the purity of the DSP/DAC clock and its affect on DAC performance.

    Let me know your thoughts.