• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 30 subscribers
  • Views 557 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320AIC3106 TDM at 96kHz Sampling

Curtis Albrecht
Prodigy 140 points
Other Parts Discussed in Thread: TLV320AIC3106

Hello!

I'm looking to use the TDM and fixed 256 bit clock setting in the 3106 Codec to achieve 96kHz sampling. If possible I could use a single SDIN/SDOUT set of lines with 4 CODECs to transmit 2, 32bit words by each codec.

2words/codec * 32bits/word * 4codecs/bus = 256bits/bus  ... seems reasonable in DSP Mode

1 Codec is master, other 3 and OMAP L138 are slave

3106 BCLK timing requirments suggest min High and Low time are 35ns each --> ~70ns period

70ns * 256 is greater than 1/96kHz period

I saw in another post that someone ran BCLK at 2048MHz, which is significantly under that minimum period.

Are these settings possible for valid operation?

-MCLK = 24.576MHz

-Fs = 96kHz --> WCLK = 96kHz

-TDM

-256BCLK/WCLK --> BCLK = 24.576MHz (Can MCLK and BCLK be the same frequency or is there a BCLK = MCLK/4 requirement)

Main concern is the maximum allowable BCLK for this codec

Thank you for any suggestions!

  • 0
    TI__Genius 9175 points

    Hello Curtis,

    You should have no problem running the setup you described. The minimum period for BCLK is not 70ns but is 20ns for IOVDD = 1.1V and 12ns for IOVDD = 3.3. This is taken from the (DIN hold time x 2) found in figure 1 in the datasheet on page 11. This allows plenty of margin for the bit clock frequency required to run 32bit TDM with a 4 device bus at a 96KHz sample rate.

    You should run the device in 256-clock mode which will run the bit clock at the necessary 256 bits per frame. More information can be found on page 25 of the datasheet.

    Regards,

    Matt

     

  • 0 in reply to Matthew Beardsworth
    Prodigy 140 points

    Thanks Matt,

    When I configure a codec to run in 256-clock mode with a 96kHz sample rate, I only get 128BCLKs per WCLK.  Do I need a 2x higher MCLK frequency to achieve this configuration?

    Currently:

    MCLK = 24.576MHz and a BCLK of 256 * 96kHz = 24.576MHz does this matter, or do I have some other configuration set incorrectly?

    Thanks,
    Curt

  • 0 in reply to Curtis Albrecht
    TI__Genius 9175 points

    Curt,

    What are you observing for your BCLK frequency?

    24.576MHz should be correct which it sounds like you are achieving. This gives 256BCLK cycles per WCLK cycle or : 8 sets of 32bit data. 4 for WCLK low and 4 for WCLK high allowing for 4 stereo channels to be TDM.

    If you are seeing only 128BCLKs per WCLK cycle, it sounds like you might have unintentional division in the clocking tree. This could be based on the default register setup or accidently set wrong. See page 29 in the datasheet. I have an app note that may also help you HERE.

    Regards,

    Matt

     

  • 0
    Prodigy 140 points
    I was seeing 12.288MHz for BCLK.
     
    After following your direction I tried a few other configurations and have gotten it to work (I think J ).  The problem, like you said, was an incorrect divide by 2, but I was overlooking the factor because I thought that I needed to enable the ADC and DAC dual rate mode to achieve 96kHz sampling.
     
    This required that I use a Q = 4, and that divide doesn’t seem like it can be made up for anywhere else in the tree.  I now have dual rate mode shut off, Q = 2, Fsref = 24.576MHz/(128 * 2) = 96kHz, this gives me a BCLK = 24.576MHz.
     
    Register 7 has Fs = 44.1 or 48, does this affect the clock tree or is it strictly for the AGC signal path?
     
    Thanks again!
     
    From: Matthew Beardsworth [mailto:bounce-4078088@mail.e2e.ti.com]
    Sent: Thursday, October 02, 2014 11:13 AM
    To: AudioConvertersForum@mail.e2e.ti.com
    Subject: RE: [Audio Converters Forum] TLV320AIC3106 TDM at 96kHz Sampling
     

    Curt,

    What are you observing for your BCLK frequency?

    24.576MHz should be correct which it sounds like you are achieving. This gives 256BCLK cycles per WCLK cycle or : 8 sets of 32bit data. 4 for WCLK low and 4 for WCLK high allowing for 4 stereo channels to be TDM.

    If you are seeing only 128BCLKs per WCLK cycle, it sounds like you might have unintentional division in the clocking tree. This could be based on the default register setup or accidently set wrong. See page 29 in the datasheet. I have an app note that may also help you HERE.

    Regards,

    Matt

     

  • 0 in reply to Curtis Albrecht
    TI__Genius 9175 points

    Register 7 is strictly controls the AGC and should not have effect on your desired timing.

    -Matt