I am finishing-up my code and noticed numerous mistakes in the register map in document SLOS602A (datahseet for AIC3204).
Two of the mistakes that concern me at the moment are the following:
P0_R91/R92
Register 91 (Left channel AGC control register 6):
Bits D7-D5: Reserved, leave as 000x xxxx
Bits D4-D0: The binary values don't make sense. If you set these bits to xxx0 0001, it sets the noise debounce time to 0. But then, if you make the calculations, and set xxx0 0010, it sets the debounce time to 4. So far, so good. But then, since there are 31 combinations, not all combinations are listed. The next in line after <4> is 1024 which, in the docs, indicate that it is value xxx0 1010. That's the problem. If every increase of 1 at the binary level is multipled by 2 at the ADC WCLK level, the table should read like this if it was fully printed in the docs:
xxx0 0001: 0
xxx0 0010: 4 ADC WCLK
xxx0 0011: 8 ADC WCLK
xxx0 0100: 16 ADC WCLK
xxx0 0101: 32 ADC WCLK
xxx0 0110: 64 ADC WCLK
xxx0 0111: 128 ADC WCLK
xxx0 1000: 256 ADC WCLK
xxx0 1001: 512 ADC WCLK
xxx0 1010: 1024 ADC WCLK >>>> ERROR: Docs say that this value is 2048 ADC WCLK
xxx0 1011: 2048 ADC WCLK >>>> ERROR: Docs say that this value is 4096 ADC WCLK
And it's all wrong from here on-end. So this means that a value of xxx1 1111 should be what? 20*4096 ADC WCLK as opposed to what's stated in the docs as 21*4096 ADC WCLK?
Register 92 (Left channel AGC control register 7): It's the same idea.
Bits D7-D4: Reserved, leave as 0000 xxxx
Bits D3-D0: Only the binary values for 0,4 and 8 are printed. Then it skips to 1024 which, in the docs, say that this is xxxx 1001. But if you follow the binary logic starting from the begining, it should read like this:
xxxx 0001: 0
xxxx 0010: 4 ADC WCLK
xxxx 0011: 8 ADC WCLK
xxxx 0100: 16 ADC WCLK
xxxx 0101: 32 ADC WCLK
xxxx 0110: 64 ADC WCLK
xxxx 0111: 128 ADC WCLK
xxxx 1000: 256 ADC WCLK
xxxx 1001: 512 ADC WCLK >>>> ERROR: Docs say that this value is 1024 ADC WCLK
xxxx 1010: 1024 ADC WCLK >>>> ERROR: Docs say that this value is 2048 ADC WCLK
xxxx 1011: 2048 ADC WCLK >>>> ERROR: Docs say that this value is 4096 ADC WCLK
And again, it's all wrong from here on-end. So this means that a value of xxxx 1111 should be what? 5*2048 ADC WCLK as opposed to what's stated in the docs as 6*4096 ADC WCLK.
Can someone please confirm the above? The reason I noticed and that I am asking is because I am pushing the CODEC settings over IP to an application and it should be very simple logic to position a slider object at the right location but the calculations only work for the first few values... afterwards, it doesn't match-up to the documentation.
