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SRC4192 PLL Lock-up Time and Necessary Time to be Stable as Sample Rate Converter

Sadanori Kato
Guru 36490 points
Other Parts Discussed in Thread: SRC4192, SRC4193

Hi,

Could you please tell us the pll lock-up time and the necessary time to be stable as the sample rate converter for SRC4192?
When does the pll lock up in the reference clock block if RCKI is input to SRC4192 and RST is assert low to high?
Moreover, when does the rate estimator block stably work as the sample rate converter if the internal REFCLK is stable and SDIN is input to SRC4192?

Best Regards,
Kato

  • 0
    TI__Mastermind 27850 points

    Hi Kato-san,

    The SRC4192 requires a 500 ms delay after the rising edge of the reset line before the part is ready to have commands sent to it. At 500 ms after the rising edge RST I believe that all systems will be operational.

    This is detailed in the Reset and Power Down Operation section in the data sheet.

    Justin

  • 0 in reply to Justin Bohr
    Guru 36490 points

    Hi Justin-san,

    Thank you for your quick response.
    Is my understanding correct although I believe that the timing constraint of 500ms which you said is necessary for the software control of SRC4193 ?
    Could you please give me your advice since I would like to grasp the timing constraint for SRC4192 ?

    Best Regards,
    Kato

  • 0 in reply to Sadanori Kato
    TI__Mastermind 27850 points
    Hi Kato-san,

    You are correct that the 500 ms delay is for writing commands to the device. The PLL and rate estimator have the pins LOCK and RDY to identify when they are operating correctly if a clk/data is applied. The times from reset to these systems being ready will vary with the audio rate. Since the times will vary we give the pins to indicate when the systems are ready.

    Justin
  • 0 in reply to Justin Bohr
    Guru 36490 points

    Hi Justin-san,

    Thank you for your support.
    Should the timing constraint for writing commands to the device be applied to both of SRC4192 and SRC4193 ?
    I believe that should be applied to SRC4193 only since that is mentioned on page 17 of the data sheet as below, you should update the data sheet if that of 500ms should be applied to SRC4192.
    Could you please give me your advice about it?

    Best Regards,
    Kato

  • 0 in reply to Sadanori Kato
    Guru 36490 points

    Hi Justin-san,

    Do you have any updates on this question?
    Your quick response would be greatly appreciated.

    Best Regards,
    Kato

  • 0 in reply to Sadanori Kato
    TI__Mastermind 27850 points

    Hi Kato-san,

    You are correct that the 500ms delay is for SPI commands which is only available  on the SRC4193. And the LOCK and RDY pins will let you know when the part has locked the PLL and when the rate estimator has also locked on.

    Justin

  • 0 in reply to Justin Bohr
    Guru 36490 points

    Hi Justin-san,

    Thank you for your support.
    I understood and will contact you if I have any questions.

    Best Regards,
    Kato