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DIX4192 MCLK synchronization

Kei Sato73562
Expert 2310 points
Other Parts Discussed in Thread: DIX4192

Hello,

I have some question of DIX4192.

When I use portB as a slave, is it necessary to synchronize it with MCLK?

If PortB aren't synchronizing with MCLK, does data will be dropped?

Input: Port B

Output: SPDIF(Tx)

Best Regards,

 

  • 0
    TI__Mastermind 27850 points
    Hi Kei,

    When operating a port in slave mode the MCLK should be synchronized with the Master device, usually the MCLK would come from the Master device.

    Justin
  • 0 in reply to Justin Bohr
    Expert 2310 points

    Hi Justin,

    Thank you for reply.

    Datasheet say

    "In Slave mode, the ports do not require a master clock because the left/right word and

    bit clocks are inputs, sourced from an external audio device serving as the serial bus timing master."

    There is mention mentioned above.

    I thought that MCLK was not necessary.

    However, it was necessary to input MCLK from a external audio device and understood when it was necessary to synchronize BCK and LRCK and MCLK.

    Best Regards,

    Kei

  • 0 in reply to Kei Sato73562
    Expert 2310 points
    Hi Justin,

    I have some question for synchronization of DIX4192.
    Is the following understanding right?

    Case 1
    Input : PortB
    Output : DIT
    It is necessary for BCK and LRCK of PortB to synchronize it with MCLK.

    Case 2
    Input : DIR
    Output : PortA
    It is necessary to choose Reference CLK(RXCKI or MCLK) which DIR chooses as a master clock of PortA.

    Case 3
    Input : PortA
    Output : PortB
    It is necessary for BCK and LRCK of PortA to synchronize it with Reference CLK(RXCKI or MCLK) which PortB chose.

    Case 4
    Input : DIR
    Output : DIT
    The master clock of DIR chooses MCLK.


    Best Regards,

    Kei
  • 0 in reply to Kei Sato73562
    TI__Mastermind 27850 points
    Hi Kei,

    I am going to try and test this today on an EVM and will get back to you with the results.

    Justin