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How to configure AIC3105/AIC3204 at 8 KHz sampling rate

Nicolas Deup
Intellectual 590 points
Hi, My codec is in master mode, Master Clock is 12.00 MHz. I would like to have bith DAC and ADC at a excat 8 KHz sampling rate. Can you help me please regarding configuration to set in the codec ? Thanks
  • 0
    TI__Guru 57800 points

    Hello Nicolas,

    For AIC3105 with MCLK of 12MHZ and a desired DAC/ADC sampling frequency of 8KHz, first you need to have a proper sampling frequency for the codec (48KHz).

    If MCLK is 12MHz, then you need to enable PLL and set their values as follows:

    Then, in order to achieve an exact sampling frequency of 8KHz in DAC and ADC, you need to set NDAC and NADC with a value of 6 (48KHz / 6 = 8KHz). this is set in Codec Sample Rate Select Register (Page 0/Register 2).

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Nicolas Deup
    Intellectual 590 points
    Diego,

    With the configuration above, I get a 7.57 KHz word clock rather than 8 KHz.
    I am sure about D value converted in hex because I use the 3105 EVM board to get the settings for this regsiter.
    Any idea about this issue please ?

    Thanks.

    Nicola
  • 0 in reply to Nicolas Deup
    TI__Guru 57800 points

    Hello Nicolas,

    If you are using TLV320AIC3105EVM with USBMODEVM, the MCLK signal generated from the motherboard has an approximated frequency of  11.28MHz. If you configure the device with the given values, the ADC and DAC sampling frequency will be close to 7.5KHz. If you want to achieve the 8KHz sampling frequency with the EVM, you need to use an external MCLK or change the values of the PLL constants.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Intellectual 590 points
    Diego, If fact I am using the USBMODEVM to power my AIC3105 and get MCLK. I thought that it was a 12 MHz and not 11.28 MHz. (11.28/12) * 8 = 7.52, so its look fine. Regards,