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TLV320AIC3254 fairly sure DIN->DAC routing in SLAA408A but not certain enough ADC->DOUT

Other Parts Discussed in Thread: TLV320AIC3254

Reading the register definitions (starting on page 95 of DS), and reading the through the 'scripts' in chapter 4, I have fair confidence that the default settings have DIN routed in stereo to DAC until configuration steps are taken to break that.

Reading one of the scripts in chapter 4 gives me the impression that MICPGA may be routed to DOUT by default but I can't see confirming details in the register definitions and trying for the life of me to find anything in the datasheet which makes configuring the source of DOUT as direct from ADC or direct from MICPGA or anything other than some clocks (and a secondary audio interface which isn't detailed abundantly either, afaict) is starting to hurt my head.

Please forgive (1) my tired eyes and (2) my boss for not even handing me hardware yet but telling me he expects results moments after handing it to me.

If you can point out the part of SLAA408A I should have noticed by now and you do I will be embarrassed but very grateful none-the-less.

If you can link something Google (or TI search mechanism) would have shown me for a 'sensible query' I will very grateful to know your search term(s) as well as, of course, for the link.

  • Hi Robert,

    Below is a 'master' script that configures the entire device for IN1->MicPGA->ADC->DOUT and also for DIN->DAC->HP.

    It assumes a master clock = 256*WCLK, I2S slave. It also assumes that the internal analog LDO (ALDO) is not used (i.e. all supplies are provided externally. If the clocks are different in your system, modify the clock settings. The AIC3254 CS software has a PLL calculator that you can use to calculate the required divider values.

    More info can be found here:

    e2e.ti.com/.../2733.tlv320aic32xx-aic36-dac32xx

    e2e.ti.com/.../2740.where-can-i-find-example-scripts-for-these-codecs

    ###############################################
    # Software Reset
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Initialize the device through software reset
    w 30 01 01
    #
    ###############################################
    
    
    
    ###############################################
    # Clock and Interface Settings
    # ---------------------------------------------
    # The codec receives: MCLK = 12.288 MHz,
    # BLCK = 3.072 MHz, WCLK = 48 kHz
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # PLL_clkin = MCLK, codec_clkin = PLL_CLK,
    # PLL on, P=1, R=1, J=8, D=0000
    w 30 04 03 91 08 00 00
    #
    # NDAC = 2, MDAC = 8, dividers powered on
    w 30 0b 82 88
    #
    # DOSR = 128
    w 30 0D 00 80
    #
    # NADC = 2, MADC = 8, dividers powered on
    w 30 12 82 88
    #
    # AOSR = 128
    w 30 14 80
    #
    ###############################################
    
    
    
    ###############################################
    # Configure Power Supplies
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # Disable weak AVDD in presence of external
    # AVDD supply
    w 30 01 08
    #
    # Enable Master Analog Power Control
    w 30 02 00
    #
    # Set the input power-up time to 3.1ms (for ADC)
    w 30 47 32
    #
    # Set the REF charging time to 40ms
    w 30 7b 01
    #
    ###############################################
    
    
    
    ###############################################
    # Configure Processing Blocks
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # PRB_P2 and PRB_R2 selected
    w 30 3C 02 02
    #
    ###############################################
    
    
    
    ###############################################
    # Configure ADC Channel
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # Route IN1L to LEFT_P with 20K input impedance
    w 30 34 80
    #
    # Route CM1L to LEFT_M with 20K input impedance
    w 30 36 80
    #
    # Route IN1R to RIGHT_P with 20K input impedance
    w 30 37 80
    #
    # Route CM1R to RIGHT_M with 20K input impedance
    w 30 39 80
    #
    # Unmute Left MICPGA, Gain selection of 6dB to
    # make channel gain 0dB, since 20K input
    # impedance is used single ended
    w 30 3b 0c
    #
    # Unmute Right MICPGA, Gain selection of 6dB to
    # make channel gain 0dB, since 20K input
    # impedance is used single ended
    w 30 3c 0c
    #
    # Select Page 0
    w 30 00 00
    #
    # Power up LADC/RADC
    w 30 51 c0
    #
    # Unmute LADC/RADC
    w 30 52 00
    #
    ###############################################
    
    
    
    ###############################################
    # Configure DAC Channel
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # De-pop: 5 time constants, 6k resistance
    w 30 14 25
    #
    # Route LDAC/RDAC to HPL/HPR
    w 30 0c 08 08
    #
    # Power up HPL/HPR
    w 30 09 30
    #
    # Unmute HPL/HPR driver, 0dB Gain
    w 30 10 00 00
    #
    # Select Page 0
    w 30 00 00
    #
    # DAC => 0dB
    w 30 41 00 00
    #
    # Power up LDAC/RDAC
    w 30 3f d6
    #
    # Unmute LDAC/RDAC
    w 30 40 00
    #
    ###############################################

    Regards,

    J-

  • Thanks anyway J, but I solved this problem days ago.

    The hardware arrived and sure enough my first attempt demonstrated that DIN->DAC->LO+HP worked as I expected and initially LI->MICPGA->ADC->DOUT was not working but a little experimentation, re-reading the example scripts and many related register definitions, and having a play with Purepath Studio led me to a completely working configuration.

    FYI: I am using the PLL and calculating the values for 96K sampling (with reasonable OSR etc) from 24.576MHz MCLK was very very easy by comparison to being sure about certain aspects of routing in this device. For supply I have only LDOIN=3.3V and my processor of choice for this application is acting as the I2S bus master - your suggested scripts wouldn't do much if I did go to the bother of implementing them and, as I am not using your EVM (nor anything other than TLV320AIC3254 from you), that would be a fair bit of bother.


    TI documentation for these codecs are not well written tho I will admit that if I knew every last detail about them as intimately as I know the back of my hands I would probably write something even less helpful as my best attempt - these scripts you people seem to like so much would be more (quickly) informative if they included at least a short name for the register being manipulated...

    ###############################################
    # Configure Power Supplies
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # Disable weak AVDD in presence of external
    # AVDD supply by setting B3 in PCR
    w 30 01 08
    #
    # Enable Master Analog Power Control
    # by clearing B3 in LDOCR
    w 30 02 00

  • Hi Robert,

    Thanks for the feedback.

    Yes, I agree in everything you said. The thing with scripts is to get a good balance between verbosity and brevity. If there is too much text, then it might become overwhelming. I'm thinking perhaps having comments such as 'set bit Dx to turn off x function, clear for y function' or something similar for commonly used features.

    Best Regards,
    J-