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PCM1795 OS[1:0] in external digital filter mode

Other Parts Discussed in Thread: PCM1795

 

Hello

Customer is using their own external Digital Filter and use PCM1795 as
external digital filter mode (DFTH=1).

Customer want to have questions in order to  evaluate THD&SNR again
in the various ( x4 x 8 x 16 ) OS[1:0] of PCM1795   in their product.

However,  to simplify the questions , Not customer's external digital filter, But
standard digital filter such  DF1706,  we want to know the relationship between
THD and OS[1:0}, and also SNR and OS{1:0].
Its  Okay not DF1706, but you have other standard external digital filter.


condition on PCM1795

DFTH= 1

fs 44.1K/ 24bit
WDCLK= fs x 8 =352.8KHz (ex DF1706)
BCLK= 11.2896MHz
System clock= 512fs

OS{1:0] =00 or 10 (x8 x 16)


Question1
How is the difference ( in dB) of THD in case  between  OS=x8 and x 16 ?
Don't you have the actual data in house?


Question2
How is the difference ( in dB) of SNR  in case between OS=x8 and x 16 ?
Don't you have the actual data in house?


Question3
I am sorry to essential questions  like another person had same question (Appendix)
But, Please let me know the meaning  about the description in PCM1795 page 45 below(*)..

Why system clock should be x 256 in case x8 (external) x 16(OS[1:0]) =128 ?
If BCLK =11.2896MHz, then system clock should be 22.5792MHz.?
I don't know the criteria about the description in the data sheet below.

My understanding of (*) is;
x8 (external) x 16(OS[1:0]) =128, and if fs were over 100KHz, then the limitation of
BCLK is 128*100KHz > 12.8MHz, then system clock should be over 256 fs ( over 25.6MHz )

 

>The effective oversampling rate is determined by the oversampling performed by both the
>external digital filter and the ΔΣ modulator. For example, if the external digital filter is 8×
>oversampling, and OS[1:0] = 00 is selected, then the ΔΣ modulator oversamples by 8×,
>resulting in an effective oversampling rate of 64×.
>(*)The 16× WDCK oversampling rate is not available above a 100-kHz sampling rate.
>If the oversampling rate selected is 16×WDCK, the system clock frequency must be over 256 fS.


(Appendix)
http://e2e.ti.com/support/data_converters/audio_converters/f/64/t/242041

 

 

 

 

 

  • Hi Kanji,

    We do not have the data in house and will have to test this. However, The current EVMs I have to test this do not allow for a robust connection between the boards to perform reliable testing for external filter mode. I will get back to you when I have more information of testing this.

    Justin
  • Deat Justin san

    Thank you for your reply.

    We will waiting your result.

    Thank you and with my best regards

  •  

    Hello Justin-san,

    Would you please adivse following ( I had  already asked you ) ?

    My cutomer is pushed me.

    ~~~~~~~~~~~~~~~~~~~~

    Question3
    I am sorry to essential questions  like another person had same question (Appendix)
    But, Please let me know the meaning  about the description in PCM1795page 45 below(*)..

    Why system clock should be x 256 in case x8 (external) x 16(OS[1:0]) =128 ?
    If BCLK =11.2896MHz, then system clock should be 22.5792MHz.?
    I don't know the criteria about the description in the data sheet below.

    My understanding of (*) is;
    x8 (external) x 16(OS[1:0]) =128, and if fs were over 100KHz, then the limitation of
    BCLK is 128*100KHz > 12.8MHz, then system clock should be over 256 fs ( over 25.6MHz )

     

    >The effective oversampling rate is determined by the oversampling performed by both the
    >external digital filter and the ΔΣ modulator. For example, if the external digital filter is 8×
    >oversampling, and OS[1:0] = 00 is selected, then the ΔΣ modulator oversamples by 8×,
    >resulting in an effective oversampling rate of 64×.
    >(*)The 16× WDCK oversampling rate is not available above a 100-kHz sampling rate.
    >If the oversampling rate selected is 16×WDCK, the system clock frequency must be over 256 fS.


    (Appendix)
    http://e2e.ti.com/support/data_converters/audio_converters/f/64/t/242041

     

     

  •  

    Hello Justin-san,

    Would you please le me know about my  Question 3 also?


    Question3

    I am sorry to essential questions  like another person had same question (Appendix)
    But, Please let me know the meaning  about the description in PCM1795 page 45 below(*)..

    Why system clock should be x 256 in case x8 (external) x 16(OS[1:0]) =128 ?
    If BCLK =11.2896MHz, then system clock should be 22.5792MHz.?
    I don't know the criteria about the description in the data sheet below.

    My understanding of (*) is;
    x8 (external) x 16(OS[1:0]) =128, and if fs were over 100KHz, then the limitation of
    BCLK is 128*100KHz > 12.8MHz, then system clock should be over 256 fs ( over 25.6MHz )

     

    >The effective oversampling rate is determined by the oversampling performed by both the
    >external digital filter and the ΔΣ modulator. For example, if the external digital filter is 8×
    >oversampling, and OS[1:0] = 00 is selected, then the ΔΣ modulator oversamples by 8×,
    >resulting in an effective oversampling rate of 64×.
    >(*)The 16× WDCK oversampling rate is not available above a 100-kHz sampling rate.
    >If the oversampling rate selected is 16×WDCK, the system clock frequency must be over 256 fS.


    (Appendix)
    http://e2e.ti.com/support/data_converters/audio_converters/f/64/t/242041

     

  •  

    Hello Justin-san,

    My customer is  in the pre-production stage for their SACD-Player, and they pushes me

    Would you please let me know about my question Question1~Question3 soon ?

    I am sorry to bother you, but please give me any reply.

     

  • Hi, Shibatani--san,

    We have attempted to find further information on your question, but unfortunately, we are unable to find it.

    So, I'm afraid you will have to make your own decisions based on the data from your system.

    D2
  • Dear Don-san,

    Thank you for your reply .

    I will discuss with TI-Japan Local FAE.

    Thanks and with my best regards