Hi,
I am having trouble configuring the AIC3254 for my application. I have been able to get my process flow to work fine using the AIC3254EVM-K with PurePath Studio, but trying to transition to my application, I cannot seem to get the PLL working. I am supplying a 20MHz clock at MCLK, and configuring the PLL and various dividers for a 32kHz sampling frequency. This is a pure acquisition application so both mini DSPs are being used for filtering ADC input. Here is my configuration, which I adapted from the original PPS output for my process flow. Note, if I change register 25 to value 0, I can see my 20MHz clock at MISO, but when I try any other value for register 25, I see nothing at MISO. This leads me to believe that I have not successfully configured and started the PLL. Any idea what I am doing wrong?
reg_value SSB_REG_Section_program[] = {
{ 0,0x00}, // # reg[ x][ 0] = 0x00 ; Switch to page 0
{ 1,0x01}, // # reg[ 0][ 1] = 0x01 ; Initialize the device through software reset
{254,0x0A}, // Delay for 10 units
{ 0,0x01}, // # reg[ x][ 0] = 0x01 ; Switch to page 1
{ 1,0x08}, // # reg[ 1][ 1] = 0x08 ; Power up AVDD LDO; Disable weak AVDD to DVDD connection; Enable Master Analog Power Control, AVDD LDO Powered; Disable weak AVDD to DVDD connection
{ 2,0x00}, // # reg[ 1][ 2] = 0x00 ; Enable Master Analog Power Control
{ 71,0x32}, // # reg[ 1][ 71] = 0x32 ; Set the input power-up time to 3.1ms
{123,0x01}, // # reg[ 1][123] = 0x01 ; Set REF charging time to 40ms (automatic)
{255,0x00}, // Load miniDSP_A_reg_values[]
{255,0x01}, // Load miniDSP_D_reg_values[]
{ 0,0x00}, // # reg[ x][ 0] = 0x00 ; Switch to page 0
{ 60,0x00}, // # reg[ 0][ 60] = 0xC0 ; miniDSP_A and miniDSP_D powered up together, miniDSP_D powered if ADC is powered, miniDSP_D used for signal processing
{ 61,0x00}, // # reg[ 0][ 61] = 0x00 ; Use miniDSP_A for signal processing
{ 17,0x08}, // # reg[ 0][ 17] = 0x08 ; 8x Interpolation
{ 23,0x04}, // # reg[ 0][ 23] = 0x04 ; 4x Decimation
{ 15,0x03}, // # reg[ 0][ 15] = 0x03 ; miniDSP_D IDAC(14:8) = 0x03, miniDSP_D IDAC = 904
{ 16,0x88}, // # reg[ 0][ 16] = 0x88 ; miniDSP_D IDAC( 7:0) = 0x88, miniDSP_D IDAC = 904
{ 21,0x03}, // # reg[ 0][ 21] = 0x03 ; miniDSP_A IADC(14:8) = 0x03, miniDSP_D IADC = 904
{ 22,0x88}, // # reg[ 0][ 22] = 0x88 ; miniDSP_A IADC( 7:0) = 0x88, miniDSP_A IADC = 904
{ 0,0x08}, // # reg[ x][ 0] = 0x08 ; Switch to page 8
{ 1,0x04}, // # reg[ 8][ 1] = 0x04 ; adaptive mode for ADC
{ 0,0x00}, // # reg[ x][ 0] = 0x00 ; Switch to page 0
{ 5,0x91}, // # reg[ 0][ 5] = 0x91 ; PLL powered up, PLL P=1, PLL R=1
{ 6,0x04}, // # reg[ 0][ 6] = 0x04 ; PLL J=4
{ 7,0x23}, // # reg[ 0][ 7] = 0x23 ; D=9152 (MSB)
{ 8,0xC0}, // # reg[ 0][ 8] = 0xC0 ; D=9152 (LSB)
{ 4,0x03}, // # reg[ 0][ 4] = 0x03 ; PLL_CLKIN = MCLK, CODEC_CLKIN = PLL_CLK
{ 12,0x8C}, // # reg[ 0][ 12] = 0x8C ; MDAC = 12, divider powered on
{ 13,0x00}, // # reg[ 0][ 13] = 0x00 ; DOSR = 128 (MSB)
{ 14,0x80}, // # reg[ 0][ 14] = 0x80 ; DOSR = 128 (LSB)
{ 18,0x02}, // # reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
{ 19,0x0C}, // # reg[ 0][ 19] = 0x0C ; MADC = 12, divider powered off
{ 20,0x80}, // # reg[ 0][ 20] = 0x80 ; AOSR = 128
{ 11,0x82}, // # reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
{ 25,0x07}, // # reg[ 0][ 25] = 0x07 ; CDIV_CLKIN = ADC_MOD_CLK
{ 26,0x81}, // # reg[ 0][ 26] = 0x81 ; CLKOUT M divider powered up, M = 1
{ 55,0x06}, // # reg[ 0][ 55] = 0x06 ; MISO is CLKOUT output (for debug)
{ 27,0x0C}, // # reg[0][27] = 0x0C ; BCLK and WCLK are output from device
{ 29,0x03}, // # reg[0][29] = 0x03 ; BDIV_CLKIN = ADC_MOD_CLK
{ 33,0x10}, // # reg[0][33] = 0x10 ; WCLK Output = Generated ADC_Fs
{ 0,0x01}, // # reg[ x][ 0] = 0x01 ; Switch to page 1
{ 51,0x40}, // # reg[ 1][ 51] = 0x40 ; Mic Bias enabled, Source = Avdd, 1.25V
{ 52,0x40}, // # reg[ 1][ 52] = 0x40 ; Route IN2L to LEFT_P with 10K input impedance; Route CM1L to LEFT_M with 10K input impedance; Route IN2R to RIGHT_P with 10K input impedance; Route IN1L to LEFT_P with 10K input impedance
{ 54,0x40}, // # reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance
{ 55,0x40}, // # reg[ 1][ 55] = 0x40 ; Route IN1R to RIGHT_P with 10K input impedance
{ 57,0x40}, // # reg[ 1][ 57] = 0x40 ; Route CM1R to RIGHT_M with 10K input impedance
{ 59,0x00}, // # reg[ 1][ 59] = 0x00 ; Enable MicPGA_L Gain Control, 0dB
{ 60,0x00}, // # reg[ 1][ 60] = 0x00 ; Enable MicPGA_R Gain Control, 0dB
{ 0,0x00}, // # reg[ x][ 0] = 0x00 ; Switch to page 0
{ 81,0xC0}, // # reg[ 0][ 81] = 0xc0 ; Power up LADC/RADC
{ 82,0x00}, // # reg[ 0][ 82] = 0x00 ; Unmute LADC/RADC
{ 0,0x01}, // # reg[ x][ 0] = 0x01 ; Switch to page 1
{ 20,0x25}, // # reg[ 1][ 20] = 0x25 ; De-pop: 5 time constants, 6k resistance
{ 12,0x08}, // # reg[ 1][ 12] = 0x08 ; Route LDAC to HPL
{ 13,0x08}, // # reg[ 1][ 13] = 0x08 ; Route RDAC to HPR
{ 14,0x08}, // # reg[ 1][ 14] = 0x08 ; Route LDAC to LOL
{ 15,0x08}, // # reg[ 1][ 15] = 0x08 ; Route LDAC to LOR
{ 0,0x00}, // # reg[ x][ 0] = 0x00 ; Switch to page 0
{ 63,0xD4}, // # reg[ 0][ 63] = 0xd4 ; Power up LDAC/RDAC w/ soft stepping
{ 0,0x01}, // # reg[ x][ 0] = 0x01 ; Switch to page 1
{ 16,0x00}, // # reg[ 1][ 16] = 0x00 ; Unmute HPL driver, 0dB Gain
{ 17,0x00}, // # reg[ 1][ 17] = 0x00 ; Unmute HPR driver, 0dB Gain
{ 18,0x00}, // # reg[ 1][ 18] = 0x00 ; Unmute LOL driver, 0dB Gain
{ 19,0x00}, // # reg[ 1][ 19] = 0x00 ; Unmute LOR driver, 0dB Gain
{ 9,0x3C}, // # reg[ 1][ 9] = 0x3c ; Power up HPL/HPR and LOL/LOR drivers
{ 0,0x00}, // # reg[ x][ 0] = 0x00 ; Switch to page 0
{ 64,0x00}, // # reg[ 0][ 64] = 0x00 ; Unmute LDAC/RDAC
// # reg[0][82] = 0
{ 82,0x00},
// # reg[0][83] = 0
{ 83,0x00},
// # reg[0][86] = 32
{ 86,0x20},
// # reg[0][87] = 254
{ 87,0xFE},
// # reg[0][88] = 0
{ 88,0x00},
// # reg[0][89] = 104
{ 89,0x68},
// # reg[0][90] = 168
{ 90,0xA8},
// # reg[0][91] = 6
{ 91,0x06},
// # reg[0][92] = 0
{ 92,0x00},
// # reg[0][84] = 0
{ 84,0x00},
// # reg[0][94] = 32
{ 94,0x20},
// # reg[0][95] = 254
{ 95,0xFE},
// # reg[0][96] = 0
{ 96,0x00},
// # reg[0][97] = 104
{ 97,0x68},
// # reg[0][98] = 168
{ 98,0xA8},
// # reg[0][99] = 6
{ 99,0x06},
// # reg[0][100] = 0
{100,0x00},
};
