• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 30 subscribers
  • Views 427 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

The configuration of tlvaic3104 by SDK 6.0

user4198054
Prodigy 80 points
Other Parts Discussed in Thread: TLV320AIC3104

Hi:

   My Tlvaic3104 link AM335x by i2c2,macasp0,i have finished the init of i2c2 and macasp0,But when i aplay the 123.wav,it failed,the log is :

root@am335x-evm:/test# aplay  123.wav
[ 3105.665283] +++++++++zhouqun:davinci_mcasp_startup
[ 3105.670440] ++++++++zhouqun:davinci_pcm_open
[ 3105.675048] +++++++zhouqun:allocate_sram
[ 3105.679229] ++++++++zhouqun:davinci_pcm_dma_request
Playing WAVE '123.wav' : Signed 16 bit Little Endian, Rate 44100[ 3105.692047] ++++++++zhouqun :davinci_mcasp_set_dai_fmt
 Hz, Stereo
[ 3105.697937] +++++++=zhouqun:daifmt :1000d++++++++++davinci_mcasp_hw_params
[ 3105.707550] ++++++++++++zhouqun :davinci_hw_common_param
[ 3105.713226] ++++++++zhouqun :davinci_hw_param
[ 3105.717864] +++++zhouqun :davinci_config_channel_size
[ 3105.723266] +++++++zhouqun:davinci_pcm_hw_params
[ 3105.730438] +++++++++zhouqun:davinci_pcm_prepare
[ 3105.735412] ++++++zhouqun:davinci_pcm_enqueue_dma
[ 3105.740447] ++++++zhouqun:davinci_pcm_enqueue_dma
[ 3105.746215] +++++++++zhouqun:aic3x_set_power
[ 3105.769927] +++++++zhouqun:davinci_pcm_trigger
[ 3105.774658] +++++++++zhouqun:pcm_cmd = 1
[ 3105.778839] ++++++++++++zhouqun:davinci_mcasp_trigger
[ 3105.784210] +++++++++zhouqun:mcasp_cmd = 1
[ 3105.788574] +++++++++zhouuqn :davinci_mcasp_start
[ 3105.793548] ++++++++++zhouqun:mcasp_start_tx
[ 3105.798095] ++++++++zhouqun:mcasp_set_ctl_reg
[ 3105.802734] +++++++++zhouqun:(mcasp_get_reg(regs) & val
[ 3105.808288] ++++++++zhouqun:mcasp_set_ctl_reg
[ 3105.812896] +++++++++zhouqun:(mcasp_get_reg(regs) & val
[ 3105.818450] ++++++++zhouqun:mcasp_set_ctl_reg
[ 3105.823059] +++++++++zhouqun:(mcasp_get_reg(regs) & val
[ 3105.828613] ++++++++zhouqun:mcasp_set_ctl_reg
[ 3105.833221] +++++++++zhouqun:(mcasp_get_reg(regs) & val
[ 3105.838775] ++++++++zhouqun:mcasp_set_ctl_reg
[ 3105.843383] +++++++++zhouqun:(mcasp_get_reg(regs) & val
[ 3105.899993] +++++zhouqun:davinci_pcm_pointer
aplay: pcm_write[ 3115.903869] +++++++zhouqun:davinci_pcm_trigger
[ 3115.909576] +++++++++zhouqun:pcm_cmd = 0
[ 3115.913726] ++++++++++++zhouqun:davinci_mcasp_trigger
[ 3115.919097] +++++++++zhouqun:mcasp_cmd = 0
[ 3115.923461] ++++++++++++====zhouqun :davinci_mcasp_stop
[ 3115.929016] ++++++++++++zhouqun: mcasp_stop_tx
:1710: write err[ 3115.935058] +++++++zhouqun:davinci_pcm_hw_free
or: Input/output[ 3115.939910] +++++++zhouqun:davinci_pcm_hw_free
 error
[ 3115.948822] +++++++++++zhouqun:davinci_pcm_close

when i aplay -N 123.wav the log is ：

[ 3191.979583] +++++++=zhouqun:daifmt :1000d++++++++++davinci_mcasp_hw_params
[ 3191.989227] ++++++++++++zhouqun :davinci_hw_common_param
[ 3191.994934] ++++++++zhouqun :davinci_hw_param
[ 3191.999542] +++++zhouqun :davinci_config_channel_size
[ 3192.004943] +++++++zhouqun:davinci_pcm_hw_params
[ 3192.012054] +++++++++zhouqun:davinci_pcm_prepare
[ 3192.017028] ++++++zhouqun:davinci_pcm_enqueue_dma
[ 3192.022064] ++++++zhouqun:davinci_pcm_enqueue_dma
[ 3192.027801] +++++++++zhouqun:aic3x_set_power
[ 3192.051330] +++++++zhouqun:davinci_pcm_trigger
[ 3192.056091] +++++++++zhouqun:pcm_cmd = 1
[ 3192.060241] ++++++++++++zhouqun:davinci_mcasp_trigger
[ 3192.065612] +++++++++zhouqun:mcasp_cmd = 1
[ 3192.069946] +++++++++zhouuqn :davinci_mcasp_start
[ 3192.074951] ++++++++++zhouqun:mcasp_start_tx
[ 3192.079467] ++++++++zhouqun:mcasp_set_ctl_reg
[ 3192.084106] +++++++++zhouqun:(mcasp_get_reg(regs) & val
[ 3192.089660] ++++++++zhouqun:mcasp_set_ctl_reg
[ 3192.094268] +++++++++zhouqun:(mcasp_get_reg(regs) & val
[ 3192.099792] ++++++++zhouqun:mcasp_set_ctl_reg
[ 3192.104431] +++++++++zhouqun:(mcasp_get_reg(regs) & val
[ 3192.109954] ++++++++zhouqun:mcasp_set_ctl_reg
[ 3192.114593] +++++++++zhouqun:(mcasp_get_reg(regs) & val
[ 3192.120117] ++++++++zhouqun:mcasp_set_ctl_reg
[ 3192.124755] +++++++++zhouqun:(mcasp_get_reg(regs) & val
[ 3192.181427] +++++zhouqun:davinci_pcm_pointer
[ 3192.286651] +++++zhouqun:davinci_pcm_pointer
[ 3192.391357] +++++zhouqun:davinci_pcm_pointer
[ 3192.496368] +++++zhouqun:davinci_pcm_pointer
[ 3192.601074] +++++zhouqun:davinci_pcm_pointer
[ 3192.706359] +++++zhouqun:davinci_pcm_pointer
[ 3192.811065] +++++zhouqun:davinci_pcm_pointer
[ 3192.916076] +++++zhouqun:davinci_pcm_pointer
[ 3193.020782] +++++zhouqun:davinci_pcm_pointer
[ 3193.125854] +++++zhouqun:davinci_pcm_pointer
[ 3193.230560] +++++zhouqun:davinci_pcm_pointer
[ 3193.335510] +++++zhouqun:davinci_pcm_pointer
[ 3193.440216] +++++zhouqun:davinci_pcm_pointer

  • 0
    TI__Guru* 84915 points

    Hi,

    Could you provide the register configuration of TLV320AIC3104 Codec? It could give us a better approach of this issue.

    Thank you.

    Best regards, 

    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Prodigy 80 points
    Hi,
    First thank you reply my question ,my board use lin1lp and lin1rp input,and use hplout and hprout ouput, my configuration 0f registers is below:
    /* Line1 Input control registers */
    snd_soc_write(codec,LINE1L_2_LADC_CTRL,0x04);
    snd_soc_write(codec,LINE1R_2_RADC_CTRL,0x04);

    /* ADC PGA Gain control registers */
    snd_soc_write(codec,LADC_VOL,0x00);
    snd_soc_write(codec,RADC_VOL,0x00);

    /* Codec datapath setup register */
    snd_soc_write(codec,AIC3X_CODEC_DATAPATH_REG,0x0A);

    /* DAC Power and Left High Power Output control registers */
    snd_soc_write(codec,HPLCOM_CFG,0xC0);

    /* DAC Digital control registers */
    snd_soc_write(codec,LDAC_VOL,0x00);
    snd_soc_write(codec,RDAC_VOL,0x00);

    /* Left High Power Output control registers */
    snd_soc_write(codec,DACL1_2_HPLOUT_VOL,0x80);

    /* Right High Power Output control registers */
    snd_soc_write(codec,DACR1_2_HPROUT_VOL,0x80);

    /* Left High Power Output control registers */
    snd_soc_write(codec,HPLOUT_CTRL,0x09);

    /* Right High Power Output control registers */
    snd_soc_write(codec,HPROUT_CTRL,0x09);


    /* Right High Power Output control registers */
    reg = snd_soc_read(codec,HPRCOM_CFG);
    printk("+++++++++zhouqun: HPRCOM_CFG (before)= %x\n",reg);
    snd_soc_write(codec,HPRCOM_CFG,0x06);
    reg = snd_soc_read(codec,HPRCOM_CFG);
    printk("+++++++++zhouqun: HPRCOM_CFG (after)= %x\n",reg);