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TLV320DAC3100 register settings

John Gibbs1
Prodigy 70 points
Other Parts Discussed in Thread: TLV320DAC3100

I have looked through the forum and wiki. I have read the data sheet. I am new at using an audio converter. I believe that my connections are all correct. The TLV320DAC3100 is being used as a slave. My processor is supplying the MCLK, WCLK, DIN and BCLK. What I do not understand is all of the register settings. I am having a difficult time understanding the register settings connection to the wave file settings. I would like to use the GPIO1 output to check my register settings. We are playing a wave file from an SD card. The audio is coming out of the speaker but it is speeded up.

Looking at page 48 of the datasheet how do I relate the DAC MAC and DAC_fs to the register settings? There seem to be a lot of settings that have to be correct and any one of them could cause a problem. How can I check the settings for correctness?

Can I use the GPIO1 out to check my settings?

  • 0
    TI__Guru 51346 points
    The basic clock configuration works like this:1. define your sampling rate
    2. choose an oversampling rate (use a 2^x value like 64x or 128x or 256x). The higher the number, the better the performance but the higher the power consumption and there are frequency limits (see Table 5-27)
    3. choose MDAC and NDAC so that the limits in Table 5-27 are not violated. Use the lowest possible numbers.
    4. calculate CODEC_CLKIN = Fs * DOSR * MDAC * NDAC.
    5. either supply this clock via MCLK (you will need an external clock with the exact frequency) or use the PLL to generate CODEC_CLKIN based on an existing system clock or the audio bit clock.
    You can use GPIO1 to monitor the internal clocks for debugging. See Figure 5-22 and registers P0R25, P0R26, P0R51
  • 0 in reply to Dominik Hartl11
    Prodigy 70 points

    Keep in mind I have never setup an audio DAC.

    1. What is the sampling rate based on? Is it a multiplier of the wave file frequency? I have a simple file recorded at 44.1K

    2. Don't care about power consumption or real high quality sound. So if I have 44.1K I could start with 2.8224 MHz?

    3.

    4. Is Fs the DAC_Fs in figure 5-20? What does the DAC_Fs need to be?

    5. So MCLK should be the same as CODEC_CLKIN ?

  • 0 in reply to John Gibbs1
    TI__Mastermind 21285 points

    Hi John,

    1. "Sample Rate" in this context is the audio sample rate.  In your case, 44.1KHz.
    2. 2.8224MHz would be fine.
    3.  
    4. DAC_Fs is your audio sampling rate.  
    5. It can be.  Check out the clock distribution diagram on page 48 (Figure 5-20) for some insight into clock distribution options.

  • 0 in reply to Michael S
    Prodigy 70 points

    1. Does the DAC_Fs need to be 16X the 44.1KHz? Changing the DAC_Fs only seems to change to tone or quality of the sound.

    2. Should I care about the DAC_MAC or DAC_MOD_CLK values other than how to get the correct DAC_Fs?

    3. We have experienced fast and slow audio. This is caused by the BCLK correct? We thought it was the DAC_Fs.

    In the datasheet example a wave file with fS = 44.1 kHz should have an MCLK = 11.2896 MHz and the BCLK should be 700KHz?

  • 0 in reply to John Gibbs1
    TI__Mastermind 21285 points
    This is being taken offline.