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Inverted inputs with TLV320AIC3254

Other Parts Discussed in Thread: TLV320AIC3254

Hi everyone,

I've been using the TLV320AIC3254 with 2 differential mic inputs (Left = IN2L - IN2R and Right = IN1R - IN1L) for 2+ years and it worked well upto now.

The two omnidirectional mics help for some treatment and are finally summed to the output. 

However, my last production came up with a weird inverted input (left) ! Making my mics behave as a bidirectional sensor after summing !

The PCB's are stricktly identical and the program of the PIC which configures the codec on power-up is also the same...

Here I have 2 identical boards with the same program, but they do not behave de same. Then I have to put a software -1 coef on the left channel of the last production if I want it to work as the first ones.

Where do you think it comes from ? Even the last datasheet update doesn't state anything about this...

Do you have an idea to identify the boards which need -1 within those which doesn't.  ?

  • Maxime,

    This is a strange issue. On your code, please verify that the registers below are not set to slow charge (default). You can use the values presented here.

    # Set the input powerup time
    w 30 47 32
    #
    # Set the REF charging time
    w 30 7b 01

    Regards,

    J-

  • Thanks for this advice.

    I've just verified the registters.

    My REF charging time, is the same 40ms.
    However my power-up time was set to 6,4ms and not 3,1ms... Could it make the difference ?

    Anyway, it has always had the same register setting. What's the point ?
  • Hi Maxime,

    3.1ms or 6.4ms are both ok for differential.

    There should not be a difference when it comes to polarity between chips.

    Are you using the default PRB modes or are you using a PurePath Studio process flow?

    If using a PurePath Studio process flow, can you please provide the register writes (e.g. SystemSettingsCode property of the framework). What I'd like to see is the PLL and divider settings.

    Also I would need the values of miniDSP_A Cycles, miniDSP_D Cycles and Sync Mode of the framework properties.

    Regards,
    J-
  • I use PurePath Studio, then here are the framework properties you think about :

    miniDSP_A_Cycles = 1024

    miniDSP_D_Cycles = 1024

    SynchMode = disabled

    Samplerates = 44.1kHz

    And here is the SystemSettingsCode :

    ;-----------------------------------------------------------------------------------

    ; Clock and Interface Configuration

    ;-----------------------------------------------------------------------------------

    ; USB Audio supports 8kHz to 48kHz sample rates

    ; An external audio interface is required for 88.2kHz to 192kHz sample rates

    ;-----------------------------------------------------------------------------------

    %%if (%%prop(SampleRate) == 176400 || %%prop(SampleRate) == 192000)

    reg[  0][  5] = 0x91 ; P=1, R=1, J=8

    reg[  0][  6] = 0x08 ; P=1, R=1, J=8

    reg[  0][  7] = 0x00 ; D=0000 (MSB)

    reg[  0][  8] = 0x00 ; D=0000 (LSB)

    reg[  0][  4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on

    reg[  0][ 12] = 0x88 ; MDAC = 8, divider powered on

    reg[  0][ 13] = 0x00 ; DOSR = 32 (MSB)

    reg[  0][ 14] = 0x20 ; DOSR = 32 (LSB)

    reg[  0][ 18] = 0x02 ; NADC = 2, divider powered off

    reg[  0][ 19] = 0x88 ; MADC = 8, divider powered on

    reg[  0][ 20] = 0x20 ; AOSR = 32

    reg[  0][ 11] = 0x82 ; NDAC = 2, divider powered on

    %%endif

    %%if (%%prop(SampleRate) == 88200 || %%prop(SampleRate) == 96000)

    reg[  0][  5] = 0x91 ; P=1, R=1, J=8

    reg[  0][  6] = 0x08 ; P=1, R=1, J=8

    reg[  0][  7] = 0x00 ; D=0000 (MSB)

    reg[  0][  8] = 0x00 ; D=0000 (LSB)

    reg[  0][  4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on

    reg[  0][ 12] = 0x88 ; MDAC = 8, divider powered on

    reg[  0][ 13] = 0x00 ; DOSR = 64 (MSB)

    reg[  0][ 14] = 0x40 ; DOSR = 64 (LSB)

    reg[  0][ 18] = 0x02 ; NADC = 2, divider powered off

    reg[  0][ 19] = 0x88 ; MADC = 8, divider powered on

    reg[  0][ 20] = 0x40 ; AOSR = 64

    reg[  0][ 11] = 0x82 ; NDAC = 2, divider powered on

    %%endif

    %%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000)

    reg[  0][  5] = 0x91 ; P=1, R=1, J=8

    reg[  0][  6] = 0x08 ; P=1, R=1, J=8

    reg[  0][  7] = 0x00 ; D=0000 (MSB)

    reg[  0][  8] = 0x00 ; D=0000 (LSB)

    reg[  0][  4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on

    reg[  0][ 12] = 0x88 ; MDAC = 8, divider powered on

    reg[  0][ 13] = 0x00 ; DOSR = 128 (MSB)

    reg[  0][ 14] = 0x80 ; DOSR = 128 (LSB)

    reg[  0][ 18] = 0x02 ; NADC = 2, divider powered off

    reg[  0][ 19] = 0x88 ; MADC = 8, divider powered on

    reg[  0][ 20] = 0x80 ; AOSR = 128

    reg[  0][ 11] = 0x82 ; NDAC = 2, divider powered on

    %%endif

    %%if (%%prop(SampleRate) == 32000)

    reg[  0][  5] = 0x91 ; P=1, R=1, J=8

    reg[  0][  6] = 0x08 ; P=1, R=1, J=8

    reg[  0][  7] = 0x00 ; D=0000 (MSB)

    reg[  0][  8] = 0x00 ; D=0000 (LSB)

    reg[  0][  4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on

    reg[  0][ 12] = 0x88 ; MDAC = 8, divider powered on

    reg[  0][ 13] = 0x00 ; DOSR = 192 (MSB)

    reg[  0][ 14] = 0xc0 ; DOSR = 192 (LSB)

    reg[  0][ 18] = 0x02 ; NADC = 2, divider powered off

    reg[  0][ 19] = 0x8c ; MADC = 12, divider powered on

    reg[  0][ 20] = 0x80 ; AOSR = 128

    reg[  0][ 11] = 0x82 ; NDAC = 2, divider powered on

    %%endif

    %%if (%%prop(SampleRate) == 22050 || %%prop(SampleRate) == 24000)

    reg[  0][  5] = 0x91 ; P=1, R=1, J=8

    reg[  0][  6] = 0x08 ; P=1, R=1, J=8

    reg[  0][  7] = 0x00 ; D=0000 (MSB)

    reg[  0][  8] = 0x00 ; D=0000 (LSB)

    reg[  0][  4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on

    reg[  0][ 12] = 0x88 ; MDAC = 8, divider powered on

    reg[  0][ 13] = 0x01 ; DOSR = 256 (MSB)

    reg[  0][ 14] = 0x00 ; DOSR = 256 (LSB)

    reg[  0][ 18] = 0x02 ; NADC = 2, divider powered off

    reg[  0][ 19] = 0x90 ; MADC = 16, divider powered on

    reg[  0][ 20] = 0x80 ; AOSR = 128

    reg[  0][ 11] = 0x82 ; NDAC = 2, divider powered on

    %%endif

    %%if (%%prop(SampleRate) == 16000)

    reg[  0][  5] = 0x91 ; P=1, R=1, J=24

    reg[  0][  6] = 0x18 ; P=1, R=1, J=24

    reg[  0][  7] = 0x00 ; D=0000 (MSB)

    reg[  0][  8] = 0x00 ; D=0000 (LSB)

    reg[  0][  4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on

    reg[  0][ 12] = 0x88 ; MDAC = 8, divider powered on

    reg[  0][ 13] = 0x01 ; DOSR = 384 (MSB)

    reg[  0][ 14] = 0x80 ; DOSR = 384 (LSB)

    reg[  0][ 18] = 0x02 ; NADC = 2, divider powered off

    reg[  0][ 19] = 0x98 ; MADC = 24, divider powered on

    reg[  0][ 20] = 0x80 ; AOSR = 128

    reg[  0][ 11] = 0x82 ; NDAC = 2, divider powered on

    %%endif

    %%if (%%prop(SampleRate) == 11025)

    reg[  0][  5] = 0x91 ; P=1, R=1, J=16

    reg[  0][  6] = 0x10 ; P=1, R=1, J=16

    reg[  0][  7] = 0x00 ; D=0000 (MSB)

    reg[  0][  8] = 0x00 ; D=0000 (LSB)

    reg[  0][  4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on

    reg[  0][ 12] = 0x88 ; MDAC = 8, divider powered on

    reg[  0][ 13] = 0x02 ; DOSR = 512 (MSB)

    reg[  0][ 14] = 0x00 ; DOSR = 512 (LSB)

    reg[  0][ 18] = 0x02 ; NADC = 2, divider powered off

    reg[  0][ 19] = 0xa0 ; MADC = 32, divider powered on

    reg[  0][ 20] = 0x80 ; AOSR = 128

    reg[  0][ 11] = 0x82 ; NDAC = 2, divider powered on

    %%endif

    %%if (%%prop(SampleRate) == 8000)

    reg[  0][  5] = 0x91 ; P=1, R=1, J=24

    reg[  0][  6] = 0x18 ; P=1, R=1, J=24

    reg[  0][  7] = 0x00 ; D=0000 (MSB)

    reg[  0][  8] = 0x00 ; D=0000 (LSB)

    reg[  0][  4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on

    reg[  0][ 12] = 0x88 ; MDAC = 8, divider powered on

    reg[  0][ 13] = 0x03 ; DOSR = 768 (MSB)

    reg[  0][ 14] = 0x00 ; DOSR = 768 (LSB)

    reg[  0][ 18] = 0x02 ; NADC = 2, divider powered off

    reg[  0][ 19] = 0xb0 ; MADC = 48, divider powered on

    reg[  0][ 20] = 0x80 ; AOSR = 128

    reg[  0][ 11] = 0x82 ; NDAC = 2, divider powered on

    %%endif

    reg[  0][ 29] = 0x10 ; Loopback ADC out to DAC in

    reg[  0][ 30] = 0x80 ; BCLK out is DAC CLK div by 128

    reg[  0][ 33] = 0x02 ; DOUT output = Secondary Data Input (Loopback)

    reg[  0][ 27] = 0x0C ; b0 = 0: DOUT will not be high impedance while Audio Interface is active

  • Hi,

    1. The last line, Page 0, Register 27, is being written 0x0C. Bit D1 is reserved and should be 0. Change this register to 0x01 and let me know the result.
    2. It seems that you have the digital configuration in SystemSettingsCode and perhaps the rest of the routing in your MCU, correct? Make sure that the interface is correct. In other words, make sure the BCLK divider is set correctly if using master mode and so forth.
    3. It also seems that you are sending S_DIN back to DOUT pin. However, at the same time you do an ADC to DAC loopback? My recommendation: instead of using ADC to DAC loopback, use inter-processor component in PurePath Studio.

    Regards,
    J-
  • Hi,

    Thanks for advice.

    Howevere, I don't get the first point :  page0/reg27 is written 0x0C, then D3 and D2 only are high. You advise me to put 0x01 instead, it still keeps D1 at 0 (unchanged) but it modify DOUT Impedence, BCLK and WCLK... Why ?

    I'm not sure about what I should care about with your second point...

    Finally, for your third point, I already use an interprocessor component in my process flow (A_D on the top right), then i just turned off loopback to see. It doesn't have any effect neither on the previous nor on the new production. Still got an inversion somehow (need I_83 to change opposit) !

  • Hi Maxine,

    You are right about the first point. I somehow got confused thinking 0x0C as 0x03.

    My recommendation is to try as much as you can to isolate the problem. You can accomplish this several ways:
    1. Start by creating a simple process flow: Dec4xIn > DSP_A_DSP_D > Int8xOut.
    2. Use the default SystemSettingsCode with as little modifications as you can (except for BCLK/WCLK as outputs, etc.). The default SSC will also contain analog configuration of the device as well.
    3. Connect EVM I2C lines to end-system I2C lines and download the code from #2.
    4. Input an 18kHz tone to both inputs (I assume you use 44.1k or 48k sampling) and observe output to check phase.
    5. If phase is correct, download process flow from #1 with your custom SystemSettingsCode to see if the issue is the processing or the register settings.

    Regards,
    J-