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SRC4382 Ratio readback and RDY Pin

Other Parts Discussed in Thread: SRC4382

Hello all,

I'm working with the SRC4382, and I'm trying to read back the ratio from the SRC. I use a PCB with some connectors for AES and S/PDIF. A PIC is the Host for setting the registers via I2C. PORTA is an output, PORTB is not connected.

Register 0x32 and 0x33 should show the ratio, but they both return all zeroes(0x00). The datasheet mentions: "These registers can be read back any time the RDY output is low.".

The ~RDY output is HIGH, and this will cause that register 0x32 and 0x33 are zeroes, as the SRC has not estimated the ratio yet.

The problem is that the ~RDY pin (pin 15) won't go low in any case.

I supplied an AES3 32, 44.1 or 48kHz signal via an Audio Precision1 (AP1), and the resampled signal is returned to the AP1 in the proper sample rate. I get the proper signal back. So the systems works, but PLL1 or PLL2 does not get into "slow" mode. The ~LOCK pin (pin 11) is low, meaning that PLL2 is in lock. This suggests that PLL1 is not working properly. I also tried this with an S/PDIF signal, but this does not change anything.

If PLL1 is not working properly the input data would not be sampled properly and there would be no output. So PLL1 must also be working.

I'm stuck now, as I have checked everything I was able to. All error registers show that there are no errors. 

I use a 24.5760MHz master clock, the register settings I used are shown below:

Register      Setting       Meaning
0x01            0x3F            Power: Power up all
0x07            0x10            TX control1: TX Input Data Source = DIR
0x09            0x06            TX control2: Valid bit and User data via DIR
0x0B            0x33            Interrupt masks: All interrupts on
0x0D            0x08            Reciever control: Use RX1, use MCLK
0x0F            0x22            PLL1 config: P=2, J=8, D=0 (24.576MHz clock)
0x10            0x00            PLL1 config:
0x11            0x00            PLL1 config:
0x2D           0x02            SRC Control1: Use DIR

All other registers are 0x00.

The ~RDY output is directly connected to the MUTE input, this should not cause problems. Weird thing is that the output signal via DIT is not muted.

I have checked the physical connections for errors, and there are none.

What else can I check to see what is going on? Has anyone experienced problems like this?

Thanks in advance,

Justin Vis

Edit: I have disconnected the ~RDY pin from the MUTE pin, with no result.

  • Hi Justin,

    Try putting the power-up command at the end of the register writes. What pin are you inputting 24.576 MHz into?

    Justin

  • Hi Justin, again thank you for the quick reply!

    I have set the power-up command at the end of the register writes, no effect. The 24.576MHz is connected to Pin 25: MCLK. I have measured the master clock at the input pin, photo attached:

    Note that this is measured with a digital scope and the image was saved, on analog mode the clock looks better.

    Justin Vis

  • Problem found: When I write the Port A Master clock divider (write at register:0x04 data:0x03 (for 48kHz)) the same samplerate as for the DIT and switch on Port A in register 0x03, the ratio is shown in register 0x32 and 0x33.
    In general I don't use port A in my application, so I haven't figured this before.

    Anyway, It works now!

    Thanks for the support Justin.

    Greetings,
    Justin