MIC and I2S configurations..

Hi, Venkat,

Could you provide more information about your application? Do you have a schematic or block diagram to describe your application? Additionally, do you have information about the pins connection? This is to have a better approach of your application.

Thank you.

Best regards,
Luis Fernando Rodríguez S.

hi sir,

 

here i attached my  applicationNew Microsoft Office Word Document.docx diagram..

in this diagram,

1)i am giving to  MIC input data(front MIC is Connected to IN2L and rear  MIC is connected to IN2R),than this data is sending to  ASI2(DOUT2 PIN)this DOUT2 is connected to my BLUETOOTH module IN pin

2)when ever BLUETOOTH is sending the data (from BT DOUT pin) is connected  to ASI2 (DIN2 pin),this DIN2  pin is directly routing into  HPL and HPR..

3)in my case BT is the module,it will start the process..

4)in another MIC data is directly send to  cpu(processor) via  ASI1..but  i am not sure about that time which is the master or slave..

5)my AIM is BT module is  by pass to ASI2,after that DAC is connected   head set..

  take the MIC data,this data sending to  BT module(via ASI2)   and cpu(via ASI1)...

regarding this which configurations i want..please explain clearly..as soon as possible..

Hi, Venkat,

I suggest to take a look of the example setups of the TLV320AIC3262 Reference Guide. Specially, you may take a look of the example 4.7.2 Stereo ADC Recording from IN2L/IN2R to Audio Serial Interface #2, 48kHz. It is related with your application.

I hope this helps you. If you still have questions or comments, please let me know.

Best regards,

Luis Fernando Rodríguez S.

HI  Luis,

                   Thanks  for your suggestion.. in linux stack  some dapm widgets is there,regarding this dapm widgets directly configurations is enough..

Please explain the usage of DMA  for I2S,for I2S  we are the DMA channels..but i  didn't understand the how  its works..

hi,

after recording the data,the same data is sent out via DOUT2(from ASI2,DOUT2 is connected my BT module) regarding this which path i have to select..
According to B0/p4/R23--
Book 0 / Page 4 / Register 23: Audio Serial Interface 2, ADC Input Control--describes
D[2:0} -- 101: ASI2 digital audio output data is sourced from ADC miniDSP Data Output 2

According to B0/p4/R31--
Book 0 / Page 4 / Register 31: Audio Serial Interface 2, Data Output--describes

D{1:0}--00: DOUT2 from Codec Audio Serial Interface 2 Output

please give the clarification regarding to this configurations..

my expected data is..
the MIC data is connected to ADC,after the same data is bypass to DOUT2(for ASI2)..
please give some clarification.......

hi,

after recording the data,the same data is sent out via DOUT2(from ASI2,DOUT2 is connected my BT module) regarding this which path i have to select..
According to B0/p4/R23--
Book 0 / Page 4 / Register 23: Audio Serial Interface 2, ADC Input Control--describes
D[2:0} -- 101: ASI2 digital audio output data is sourced from ADC miniDSP Data Output 2

According to B0/p4/R31--
Book 0 / Page 4 / Register 31: Audio Serial Interface 2, Data Output--describes

D{1:0}--00: DOUT2 from Codec Audio Serial Interface 2 Output

please give the clarification regarding to this configurations..

my expected data is..
the MIC data is connected to ADC,after the same data is bypass to DOUT2(for ASI2)..
please give some clarification.......

Hi, Venkat,

Book 0 / Page 4 / Register 23 is used to route ASI2 digital output to ADC miniDSP output 1, ADC miniDSP output 2, ASI1 digital input, ASI2 digital input or ASI3 digital input. Book 0 / Page 4 / Register 31 is used to route DOUT2 pin to ASI2 output, ASI1 data input, ASI2 data input or ASI3 data input.

The difference between both registers is that Register 23 refers to an internal route of ASI2 output and Register 31 refers to DOUT2 pin.

Best regards,
Luis Fernando Rodríguez S.

Hi sir,

               I have one doubt, at a time the MIC input  data is  shared to   ASI1 and ASI2 (parellely),it is possible..  

if possible means,how its works please explain me........

Hi, Venkat,

Yes, it is possible to share the same data to the ASI1 and ASI2. Please take a look of the Figure 2-81. Summary of Routing for Audio Serial Interfaces for the next explanation.

In the example  4.7.2 Stereo ADC Recording from IN2L/IN2R to Audio Serial Interface #2, 48kHz, the ASI2 is used to record from IN2L/IN2R. B0_P4_R23_D(2:0) is configured as 001 to route ADC data to Audio Serial Interface #2. B0_P4_R7_D(2:0) must be configured to route ADC data to Audio Serial Interface #1 too.

The rest of the clocks and data must be configured similar as the ASI2. I mean, BCLK1, WCLK1, DOUT1 and DIN1 must be routed to ASI1. BCLK1 must receive the same clock that BCLK2. It is the similar case of WCLK1 and WCLK2. 

I hope this helps you. If you still have questions, please let me know.

Best regards,

Luis Fernando Rodríguez S.

Hi  sir,

                         I configured all those registers,for  headset detection  software register is enough or i have trigger any interrupts.i was thinking software configuration is enough ..please give me clarity on that section..

-->the pure path software  provides  some register  buffers,i mean  base_main_Rate44_pps_driver.h files,this files  should  be required ?because i saw  some linux stacks,there he was ported this registers,here some adc & dac instructions and coefficients  related configuration is there...this source files required in my application also ? or else routing section is enough..

-->I got a amplified  diagram for TLV320aic3262, here ASI   block block is connected to  miniDSP dig mixer volume and miniDSP  miniDSP ASRC Dig mixer volume section, i  want some detailed  information regarding on this  sections,what is inside this blocks.. 

Hi, Venkat,

There's no need to configure the interrupts for the headset detection function. The interrupts can be used for this operation if you need to have a signal when the headset is detected, but it depends your application. The headset detection doesn't need the interrupts to work.

The .h files are required when you need to implement your PurePath Studio algorithm by the coefficients and instructions.

Regarding the amplified diagram, could you provide it please? This is to have a better approach of the blocks that you refer.

Thank you.

Best regards,
Luis Fernando Rodríguez S.

HI LUIS,

                     Regarding that  .h files ,I  cant able to understand the  pure path studio.I observed some example  process flow  diagrams in PPS, but still i didn't  understand what i want to exactly in PPS.

I want to Know how generate the coefficients  and instructions for the below two cases..

1.When the Mic Input data is connected to ASI1 and ASI2 ,this data will  be  send to external  Processors(BT module)as well as this data is routed to head set (for Intial testing).

2.When ever  I receive  data from  ASI2,then this data is  routed  to  headset(HPL/HPR).

Hi, Venkat,

PurePath Studio is used to generate the coefficients and instructions to generate algorithms by the internal miniDSP. If you don't need to use an additional algorithm, there's no need to generate coefficients and instructions.

For the two cases that you mention, it seems that there's no need to use PurePath Studio because you're not using the miniDSP. Do you need an additional algorithm like filters, mixers, noise reduction or something else?

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

                   ya,I am using the mixer amplifiers for initial  audio testing,now what   i am doing  is the mic data is pass to PGA amplifier  to MIXER(MAL/MAR) to  head set .. once it is happened,than i go through the audio serial interfaces..first I planed for loop back testing..

one more doubt  i have ,according to  the  previous discussions  the  ADC  output data is routed to #ASI1 and  #ASI2..at that time without minidsp(ADC coefficients) how it will work..

what i am thinking is   according to the tlv320aic3262 reference,ASI block  is connected to  minidsp ADC and DAC blocks,do to this consideration  with out  Involving of   ADC  and DAC coefficients  how its possible ...

please give me the detail description  for  routing sections of ADC to ASI ,ASI  to DAC and  MIC to  MIXER to headset..based this consideration any coefficients is required or not.....

thanking you sir..

best regards

venkat. E

Hi, Venkat,

Each ADC consists of a signal-processing engine with fixed processing blocks, a programmable miniDSP, a digital decimator (interpolation in DAC case) filter and multi-bit digital delta-sigma modulator. If the miniDSP coefficients and instructions are not required, you can select to use between the miniDSP or the signal processing blocks. Registers 60 and 61 are used to configure the ADC and DAC processing blocks.

So, you would need to route the input to the ADC (with the internal processing blocks configured), then the ADC to ASI, ASI to DAC (with the internal processing blocks configured) and DAC to headset.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

                 Thanks  Luis for you providing  the valuable suggestions and clarifications..

I tried  with this configurations but  i am not getting  any audio..

one more doubt  i have, who  will provide the MCLK,because  i tried  with  internal on chip oscillator clock..but i don't  know clocks is enabled or not.. 

here i will share the configuration file for MIC input to headset output..please give the feedback and  confirmation..

int stereo_ADC_to_DAC_playback_config()
{
//codec software reset
printf("codec software reset\n");
appI2CWrite2(0x00, 0xFF,0x00);//page0
appI2CWrite2(0x7F, 0xFF,0x00);//book 0
appI2CWrite2(0x01, 0xFF,0x01);//software reset
sp5kTimeDelay( SP5K_TIME_DELAY_1MS , 5);

printf("codec power and analog configuration\n");
//Power and Analog Configuration
appI2CWrite2(0x00, 0xFF,0x01);//Select Page 1
appI2CWrite2(0x01, 0xFF,0x00);//Disable weak AVDD to DVDD connection,make analog supplies available
appI2CWrite2(0x7A, 0xFF,0x01);//REF charging time = 40ms
appI2CWrite2(0x79, 0xFF,0x33);//Set the quick charge of input coupling cap for analog inputs
appI2CWrite2(0x22, 0xFF,0x3e);//8/8 CP sizing (Setup A)
appI2CWrite2(0x21, 0xFF,0x28);//CP divider = 4, 500kHz, Runs off 8MHz oscillator
appI2CWrite2(0x23, 0xFF,0x10);//Charge Pump to power up on Ground-Centered Headphone Power-up
appI2CWrite2(0x08, 0xFF,0x00);//Full chip CM = 0.9V
appI2CWrite2(0x03, 0xFF,0x00);//PTM_P3, High Performance
appI2CWrite2(0x04, 0xFF,0x00);//PTM_P3, High Performance

printf("codec clock configuration\n");
//clock configuration
appI2CWrite2(0x00, 0xFF,0x00);//page 0x00
appI2CWrite2(0x04, 0xFF,0x00);//set ADC_CLKIN ,DAC_CLKIN as MCK1-default
appI2CWrite2(0x12, 0xFF,0x81);//power up NADC,NADC=1
appI2CWrite2(0x13, 0xFF,0x82);//power up MADC,MADC=2
appI2CWrite2(0x14, 0xFF,0x80);//program the OSR of ADC t0 128
appI2CWrite2(0x0B, 0xFF,0x81);//NDAC=1
appI2CWrite2(0x0C, 0xFF,0x82);//NDAC=2
appI2CWrite2(0x0D, 0xFF,0x00);//program the osr of DAC t0 128
appI2CWrite2(0x0E, 0xFF,0x80);

printf("codec ASI2 configuration and Routings\n");
//ASI routing section
appI2CWrite2(0x00, 0xFF,0x04);//page4
appI2CWrite2(0x011, 0xFF,0x00);//ASI2=I2S mode,16 bit
appI2CWrite2(0x1A, 0xFF,0x00);//BCLK2 as BCK i/p,WCLK2 as wclk i/p
appI2CWrite2(0x17, 0xFF,0x01);//Route the adc data to asi2
appI2CWrite2(0x18, 0xFF,0x50);//ASI2 left & RIght channel connected to L & R DAC
appI2CWrite2(0x45, 0xFF,0x04);//wclk2 pin
appI2CWrite2(0x46, 0xFF,0x04);//bckl2 pin
appI2CWrite2(0x47, 0xFF,0x22);// dout2
appI2CWrite2(0x48, 0xFF,0x20);//din2
appI2CWrite2(0x76, 0xFF,0x16);//only ASI2 routed to DAC minidsp data input1

printf("signal processing blocks\n");
//signal processing blocks
appI2CWrite2(0x00, 0xFF,0x00);//page0
appI2CWrite2(0x3D, 0xFF,0x01);//ADC PRB mode to PRB_B1
appI2CWrite2(0x3C, 0xFF,0x01);//DAC mode to PRB_B1

printf("analog input section\n");
//ADC input channel configuration --IN2L/IN2R
appI2CWrite2(0x00, 0xFF,0x01);//page 0
//Set the input common mode to 0.9V--B0_P1_R8
appI2CWrite2(0x08,0xFF,0x00);
//MICbias enabled
appI2CWrite2(0x33,0xFF,0x44);
//Route IN2L and CM1 to LEFT ADCPGA with 20K input impedance-B0_P1_R52
appI2CWrite2(0x34,0xFF,0x20);
appI2CWrite2(0x36,0xFF,0x80);//B0_P1_R54
//Route IN2R and CM1 to RIGHT ADCPGA with 20K input impedance-B0_P1_R55
appI2CWrite2(0x37,0xFF,0x20);
appI2CWrite2(0x39,0xFF,0x80);//B0_P1_R57
//Left Channel Analog ADC PGA = 6 dB -> Overall Channel Gain of 0dB
appI2CWrite2(0x3B,0xFF,0x0C);//B0_P1_R59
//Right Channel Analog ADC PGA = 6 dB -> Overall Channel Gain of 0dB
appI2CWrite2(0x3C,0xFF,0x0C); //B0_P1_R60
//ADC Analog programmed for PTM_R4
appI2CWrite2(61,0xFF,0x00); //B0_P1_R61
appI2CWrite2(0x00, 0xFF,0x00);//page0
//Power-up ADC Channel
appI2CWrite2(0x51,0xFF,0xC0); //B0_P1_R81
//Unmute ADC channel and Fine Gain = 0dB
appI2CWrite2(0x52,0xFF,0x00); //B0_P1_R82

printf("output section route to headset\n");
//Output Channel Configuration
appI2CWrite2(0x00, 0xFF,0x00);//page0
sp5kTimeDelay( SP5K_TIME_DELAY_1MS , 2);
//power up the left & Right DAC channels--B0_p0_r63
appI2CWrite2(0x3F,0xFF,0xC0);
//unmute the DAC digital volume control--B0_p0_r64
appI2CWrite2(0x40,0xFF,0x00);
appI2CWrite2(0x00, 0xFF,0x01);//page0
// Headphone in groung centered mode,HPL gain=0db--B0_P1_R31
appI2CWrite2(0x1F,0xFF,0x80);
// HPR to have same gain as HPL set to 0db--B0_P1_R32
appI2CWrite2(0x20,0xFF,0x80);
//HP sizing 100%(headphone o/p driver stage)--B0_P1_R9
appI2CWrite2(0x09,0xFF,0x00);
//Enable DAC to HPL/R & power up HPL/R--B0_P1_R27
appI2CWrite2(0x1B,0xFF,0x33);

}

Hi, Venkat,

Actually the MCLK must be generated by an external oscillator or processor. The codec needs to generate the internal ADC/DAC clocks by an external clock. Please take a look of the Figure 2-44 Clock Distribution Tree for details.

Have you checked the DOUT pin? Could you get any data on this pin?

Best regards,

Luis Fernando Rodríguez S.

HI Luis,

                  Sorry for the delay,I am not using any MCLK till now,i am trying with Internal  codec oscillator (HF_REF_OSC).

please give clarification on  MCLK, what  is  the relation between ASI and MCLK...

-->Suppose  CODEC is master ,that time MCLK expecting the clock from Externel oscillator frequency(I mean not from the processor),why its like that..

-->for example with out MCLK1/MCLK2, any possibility is there for running the clock in CODEC.

Regards

venkat. E

Hi, Venkat,

The MCLK is used to generate the DAC and ADC sample rates. This sample rate must be the same that the WCLK frequency.

The master clock is needed when the BCLK and WCLK are configured as outputs (master mode). When the BCLK and WCLK are configured as inputs (slave mode), MCLK can be omitted. The figure 2-44 (Clock Distribution Tree) shows that the DAC and ADC sample rates can be configured by several clocks. So, MCLK can be replaced by all the options that the distribution tree shows.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

                Now  MIC data is connected  to LEFT PGA,than PGA to MIXER,to head set..here i am using HF oscillator clock but its not working..for mixer any coefficients is required ..

Clock configuration :-

printf("providing the HF_OSC_CLK\n");
appI2CWrite2(0x00, 0xFF,0x00);//page0
appI2CWrite2(0x4, 0xFF,0x77);//HF_OSC_CLK=ADC_CLK_IN,HF_OSC_CLK=DAC_CLK_IN
appI2CWrite2(0x18, 0xFF,0x0F);//HF_CLK_IN=HF_OSC_CLK

the remaining configuration are implemented from   4.2 PGA Analog Bypass to Ground-Centered Headphones..

please give me solution regarding this..

 

HI LUIS,

                In Audio Serial Interface 1, i am getting continuous  data  on    DOUT1 pin (200khz of sample rate)..how can resolve this issue..please explain me what have to implement..why its generates..

Hi, Venkat,

200 kHz is over the limit of the possible sample rate. The sample rate configuration must be changed (you can use the internal dividers to change the sample rate). Ensure that the sample frequency is configured properly.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

            The sample rate is  48 kHZ only,but    DOUT1 getting 200 kHz, I didn't understand  why i am getting the  continuous  clock pulse on DOUT1.

 my clock configurations is:

MCLK1=12.28 MHZ

BCLK1=1.536 MHZ

WCLK1=48 KHZ

for ASI1 word length is 16 bits, channels =2..

ADC & DAC sampling rates also 48 KHZ only..

but DOUT1 getting continuous  clock,that time any data send out to DOUT1 ,it should be varied but why  i got continous  pulse  on DOUT1,any noise or configuration issue is there..

thanks..

Hi, Venkat,

Could you tell me the register configuration that you're using to configure the DOUT1 pin? Book 0/ Page 4/ Register 67 is used to configure DOUT1. Have you configured DOUT1 as the ASI1 Data Output?

Best regards,
Luis Fernando Rodríguez S.