Dear support,
I am trying to use the AIC3254 as master for the Bclk and the Wclk. A 24MHz Mclk is provided externally.
I configured the registers to output these clock but these does not output.
I try first in my custom board then in the AIC3204evm, after disabling the I2S bus (SW2 bit 4).
Attached the EVM script I used. The clock section is as follow:
############################################### # Clock Setup ############################################### # # Select Page 0 w 30 00 00 # # MCLK pin is input to PLL w 30 04 03 # # PLL DIV (P) 2, R = 1 w 30 05 a1 # # PLL NDAC ON value 12 w 30 0b 8C # # PLL MDAC ON value 12 w 30 0c 81 # # PLL DOSR=125 MSB w 30 0d 0 # # PLL DOSR=125 LSB w 30 0e 7d # # MADC divider OFF w 30 13 1 # # PLL AOSR=125 MSB w 30 14 7d # # INTERFACE DSP (01) 16 bit (00) bclk out (1) wclkout (1) 00 w 30 1b 4c
I would understand why the clocks does not output.
Thank you.
aic3204bclk_wclk_master.txt
############################################### # Direct Analog Bypass # --------------------------------------------- # This script routes IN1_L/R inputs to HPL/R # outputs. Connect a portable media player # to J1 (IN1_L/R) and headphones to J9. # # Ensure the input signal does not exceed the # maximum rated input voltage. ############################################### ############################################### # Software Reset ############################################### # # Select Page 0 w 30 00 00 # # Initialize the device through software reset w 30 01 01 # ############################################### ############################################### # Initialize Codec ############################################### # # Select Page 1 w 30 00 01 # # Disable weak AVDD in presence of external # AVDD supply w 30 01 08 # # Enable Master Analog Power Control w 30 02 00 # # Set the input powerup time to 3.1ms (for ADC) # w 30 47 32 # # Set the REF charging time to 40ms w 30 7b 01 # ############################################### ############################################### # Clock Setup ############################################### # # Select Page 0 w 30 00 00 # # MCLK pin is input to PLL w 30 04 03 # # PLL DIV (P) 2, R = 1 w 30 05 a1 # # PLL NDAC ON value 12 w 30 0b 8C # # PLL MDAC ON value 12 w 30 0c 81 # # PLL DOSR=125 MSB w 30 0d 0 # # PLL DOSR=125 LSB w 30 0e 7d # # MADC divider OFF w 30 13 1 # # PLL AOSR=125 MSB w 30 14 7d # # INTERFACE DSP (01) 16 bit (00) bclk out (1) wclkout (1) 00 w 30 1b 4c ############################################### # Playback Setup ############################################### # # Select Page 1 w 30 00 01 # # De-pop w 30 14 25 # # Direct Bypass Gain = 0dB w 30 16 00 00 # # Route IN_1L/R to HPL/R w 30 0C 04 04 # # Power up HPL/HPR drivers w 30 09 30 # # Unmute HPL/HPR driver, 0dB Gain w 30 10 00 00 # ###############################################
