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TLV320AIC3204 fractional divider PLL settings

Other Parts Discussed in Thread: TLV320AIC3204

Hello,

I'd like to ask for exact formula how to calculate D register for fractional divider at TLV320AIC3204. My MCLK input is 12.5MHz and I need go get sample rates of 44.1kHz and 16kHz.

Michal

  • Hello, Michal,

    Actually these values are calculated by approximation. You may use the TLV320AIC3254EVM GUI to calculate these values in an easier way: http://www.ti.com/lit/zip/slac214 

    You only need to follow the next steps to use it:

    1. Install the AIC3254_CS_v1_2_1 software.
    2. Open the program as administrator.
    3. On the main window, select the Clocks/Interface option on the Digital Settingsmenu.

    4. This will open a new window where you can configure the PLL input clock and PLL coefficients.

    5. Then, you need to click on the dividers menu to change the dividers values and check the sample frequency result. Please notice that the CODEC_CLKIN value was calculated in the step 4.

    I hope this helps you. If you still have questions, please let me know.

    Best regards,

    Luis Fernando Rodríguez S.