• State
  • Locked Locked
  • Replies 9 replies
  • Subscribers 30 subscribers
  • Views 2155 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

tlv320aic3106 frequency response

Sreelakshmi Radhakrishnan
Intellectual 315 points
Other Parts Discussed in Thread: AM1808, TLV320AIC3106

Hi
I am using TLV320AIC3106 audio codec with AM1808 processor for a Software Defined Radio
I find that the frequency  response of the codec as observed does not meet the specifications as per the codec datasheet .
The -3dB point of the looped back audio as observed on the audio analyzer is  at 0 .27fs instead of 0 .45fs.
It could be that either the ADC or DAC or both may not be configured properly.
But the values observed at the ADC output seems to indicate  that the ADC Decimation filter may not be configured correctly or it  fails to meet the specs.
The sampling rate specified for my radio is  8KHz and the audio bandwidth is 3.5KHz.
But setting sampling rate at 8KHz attenuates frequencies from 2.18 KHz.
Kindly help me if I am missing something.
Test Setup:
To isolate the problem, I have input the ADC output to the DAC input so as to form a loopback, the loopback being done on the AM1808 processor side.(The digital o/p of ADC is looped back into the DAC input of the codec by McASP loopback on the AM1808 processor  )
In test setup,I use an audio generator to input a tone and capture the DAC output on the audio analyzer.
 
 
Audio Input is given at Line1 and Output is captured  at HPROUT.
These are my observations.
1.Sample rate of ADC and DAC set at 8 KHz, the -3dB frequency observed is at 2.18 KHz instead of 3.6 KHz
2. Sample rate of ADC and DAC set at 16 KHz, the -3dB frequency observed is at 4.28 KHz instead of 7.2 KHz
3. Sample rate of ADC and DAC set at 24 KHz, the -3dB frequency observed is at 6.57 KHz instead of 10.8 KHz
4. Sample rate of ADC and DAC set at 48KHz, the -3dB frequency observed is at 12.91 KHz instead of 21.6 KHz.
I have selected MCLK as the clock input using an onboard crystal of frequency 24.576MHz
Initially I had disabled the PLL and used the divider to obtain fsref at 48MHz.
Then to confirm the clock settings are right, I configured the PLL  to obtain fsref at 48KHz
I have verified the frequency of fsref by capturing the clock output at gpio1 for various M&N values and confirmed that clock settings are right.
Still, the observations are the same.,the -3dB point is observed as at .27fs.
These are the register settings I used for PLL
Reg 3:0xa2, Reg 04:0x10, Reg 5:0x00, Reg 6:0x00, Reg11:0x02, Reg 101:0x00,
Reg 101:0x00, Reg 98:0x20, Reg 102:0x02
(K=4,p=2,r=2)
Kindly help me if I am missing something.
 
Hi
I am using TLV320AIC3106 audio codec with AM1808 processor for a Software Defined Radio
I find that the frequency  response of the codec as observed does not meet the specifications as per the codec datasheet .
The -3dB point of the looped back audio as observed on the audio analyzer is  at 0 .27fs instead of 0 .45fs.
It could be that either the ADC or DAC or both may not be configured properly.
But the values observed at the ADC output seems to indicate  that the ADC Decimation filter may not be configured correctly or it  fails to meet the specs.
The sampling rate specified for my radio is  8KHz and the audio bandwidth is 3.5KHz.
But setting sampling rate at 8KHz attenuates frequencies from 2.18 KHz.
Kindly help me if I am missing something.
Test Setup:
To isolate the problem, I have input the ADC output to the DAC input so as to form a loopback, the loopback being done on the AM1808 processor side.(The digital o/p of ADC is looped back into the DAC input of the codec by McASP loopback on the AM1808 processor  )
In test setup,I use an audio generator to input a tone and capture the DAC output on the audio analyzer.
Analyzer In
 in
 
 
 
GEN out
 
 
 

AM1808
 
TLV320Aic3
 

                             

 

Audio Input is given at Line1 and Output is captured  at HPROUT.
These are my observations.
1.Sample rate of ADC and DAC set at 8 KHz, the -3dB frequency observed is at 2.18 KHz instead of 3.6 KHz
2. Sample rate of ADC and DAC set at 16 KHz, the -3dB frequency observed is at 4.28 KHz instead of 7.2 KHz
3. Sample rate of ADC and DAC set at 24 KHz, the -3dB frequency observed is at 6.57 KHz instead of 10.8 KHz
4. Sample rate of ADC and DAC set at 48KHz, the -3dB frequency observed is at 12.91 KHz instead of 21.6 KHz.
I have selected MCLK as the clock input using an onboard crystal of frequency 24.576MHz
Initially I had disabled the PLL and used the divider to obtain fsref at 48MHz.
Then to confirm the clock settings are right, I configured the PLL  to obtain fsref at 48KHz
I have verified the frequency of fsref by capturing the clock output at gpio1 for various M&N values and confirmed that clock settings are right.
Still, the observations are the same.,the -3dB point is observed as at .27fs.
These are the register settings I used for PLL
Reg 3:0xa2, Reg 04:0x10, Reg 5:0x00, Reg 6:0x00, Reg11:0x02, Reg 101:0x00,
Reg 101:0x00, Reg 98:0x20, Reg 102:0x02
(K=4,p=2,r=2)
Kindly help me if I am missing something.
  • 0
    TI__Guru* 84915 points
    Hi, Sreelakshmi,

    Could you provide more information about the codec configuration? Have you configured any gain in the codec? Additionally, could you provide more information about your input signal (amplitude, frequency)? It is to have a better approach of the issue.

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 315 points

    Hi Luis Fernando,

    Please find the details.

    Input settings:

    Line1L is configured as single ended. LINE1L is connected to the left ADC PGA .Input level control gain = 0dB.( Reg 19,page 0)

    Gain settings: Left ADC PGA gain settings:22dB ( Reg 15,page 0)

    Output Settings:

    DAC_L1 is routed to HPLOUT. HPLOUT Output Level Control =9dB (( Reg 51,page 0)

    Audio input level set at 35mVp.(I have captured the audio output at HPLOUT in audio analyser and verified that there is no clipping.)

    The audio input is fed at LINE1LP and the looped back audio output at HPLOUT is fed to audio analyser.

    I am attaching the schematic of the board and a screen shot of the register values of the codec for page 0 captured.

    With reference to the Schematic,I am using Handset_MIC to input the tone and Handset_SPK to capture the output.

    I would like to  know what is the passband attenuation at 0.45fs for DAC Interpolation filter.

    This is the frequency response observed.

    Input Audio Signal : 35mVp

    fs @8KHz

    fs @12KHz

    Input Audio
     Signal Freq(KHz)

    Output Amplitude 
     (mVac)

    Input Audio
     Signal Freq(KHz)

    Output Amplitude
     (mVac)

    1

    978

    1

    1014

    1.2

    950

    1.2

    1004

    1.3

    933

    1.3

    997

    1.4

    912

    1.4

    990

    1.5

    890

    1.5

    982

    1.6

    868

    1.6

    973

    1.7

    843

    1.7

    964

    1.8

    817

    1.8

    954

    1.9

    790

    1.9

    944

    2

    762

    2

    931

    2.18

    771

    2.5

    855

    2.2

    733

    2.7

    820

    2.3

    670

    3.28

    771

    2.4

    638

    3.5

    661

    2.5

    606

    4

    550

    3

    430

    5

    297

    3.6

    157

    5.4

    157

    Expecting 3dB cut off frequency at 3.6KHz (0.45fs)

    Observed 3dB cut off at 2.18 KHz

    Expecting 3dB cut off frequency at 5.4KHz (0.45fs)

    Observed 3dB cut off at 3.28 KHz

     

  • 0 in reply to Sreelakshmi Radhakrishnan
    TI__Guru* 84915 points
    Hi, Sreelakshmi,

    Have you tried to do the test with an input signal of 0.707 Vrms? Additionally, have you tried to use a gain of 0dB for Left ADC PGA and HPLOUT Output Level? I suspect the tests in the datasheet were done with these parameters.

    I already checked the schematic and it seems to be in order.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 315 points

    Hi Luis Fernando Rodríguez

    I tried to test with 0.707 mVrms with zero internal gain.but I got the same observations.

    I was using the Linux audio test application which was part of the BSP of AM1808 for audio loopback test.

    In order to isolate the LInux audio  test application application  from the test scenario,

    We tried to develop the drivers for the codec in Code composer studio using the the AM1808 evm (it has the same codec ).

    I have done the same loopback test in JTAG mode with the custom driver we developed.

    Frequency response meets the specifications.

    Now I have to implement the same in our board.

    Will keep you updated once we finish debugging in our board.

    Thank you

  • 0 in reply to Sreelakshmi Radhakrishnan
    Intellectual 315 points

    Hi Luis


    kindly view this post as a continuation of the  thread.

    I have configured the codec at 8KHz sampling rate using the custom software we developed in JTAG.

    I am feeding a sine wave of frequency 1 KHz using audio signal generator and I do McASP loopback on the processor side.(Kindly refer the test setup in the previous post for clarification)

    I get the specified response both in terms of amplitude and frequency for a range of input amplitudes from 20mVp to 80 mVp and frequency from 500 Hz to 3.4 KHz.

    I have kept the Analog PGA gain at 55 corresponding to the register value of 0x37.

    Problem Statement

    In the same setup,I tried to enable AGC.

    I have kept the target level as -5.5dB.

    It keeps the amplitude of the output ( as observed on audio loopback ) 5.5 dB down the full scale for the range of inputs 10 mVp to 80mVp.

    But I observe a fluctuation in the amplitude of the sinewave loopbacked output even though the input amplitude and frequency is kept constant.

    The amplitude varies by around 1 dB in time. Ie It goes down by 1dB , then increases to the expected level and  again go down by 1dB so on. Correspondingly  the register values  of Register 32 ie Left Channel Gain Applied by AGC Algorithm changes by 1 dB.

    I have changed the attack and decay times between both extremes..But I am not able to eliminate the fluctuation completely.

    In the same input conditions, If I disable the AGC,I get a constant amplitude output as set by the PGA gain.

    Kindly give your suggestions to eliminate the fluctuation observed.

  • 0 in reply to Sreelakshmi Radhakrishnan
    TI__Guru* 84915 points
    Hi, Sreelakshmi,

    I apologize for the late response.

    I would like to know the rest of the register configuration if it is possible. The AGC sometimes generate a wrong behavior if the codec is not configured correctly. Could you provide the entire register configuration, please? Is it the same that you provided before?

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 315 points

    Luis

    sorry about the delayed response.

    Please have a look at the register values from the text file attached. It is the test code used in the setup.

    Rest of the registers are left at the default values.

    I will consolidate the values for ease of understanding.

    1.PLL is disabled. sampling clock derived from 24.576 MHz crystal.Please refer schematic from earlier posts.clock configuration is correct since frequency response matches the specified response for different sampling rates.

    2.sampling rate for test setup set at 8KHz.

    3. left DAC datapath plays left channel input data

    4.codec configured as master.

    5.input given at Line1LP and output taken from HPLOUT.

    6. LineL1 routed to Left AGC ,Left AGC to Left ADC. the looped back digital data from left ADC fed to left DAC.DAC_L1 is routed to HPLOUT.

    7.input amplitude: 20mVp to 80 mVp

    8.input frequency range:500 to 3.4 KHz

    9. fs(ref) = 48kHz (for AGC time constant.)

    10.target level -5.5dB.

    Kindly suggest recommended values for attack and release times so that I can eliminate the fluctuation.

    TLV_Config.c.txt 
    /*####################################################################################
#
#				File Name: SDRMP_AudioCodec.c
#
#######################################################################################
#
# Project Name	        : SDR-MP
#
# Project Code			:
#
# Created				:
#
# Purpose				: Implementation of LV320AIC3106 functions for OMAP-L138.
#
# Description			:
#
# Author(s)				: Shino Samuel
#
# Version No			:
#
# Revisions				:
#
# Remarks				: Complete
#
# Copyright				: Centre for Development of Advanced Computing(C-DAC), Trivandrum - 2011
#########################################################################################*/
#include "main.h"
#include "SDRMP_McASP.h"
#include "SDRMP_Types.h"
#include "SDRMP_OMAPL138.h"
#include "SDRMP_Global.h"
#include "SDRMP_ISRs.h"
#include "SDRMP_AudioCodec.h"
uchar ReadVal[5] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF};

/*###################################################################
#
#			Function Name: AIC3106_Init
#
#####################################################################
#
#  Arguments	:
#
#  Description	:  Initialise AIC3106 codec chip.
#
#  Return Type	:  int
#
#  Remarks		:  complete
#
###################################################################*/

#define AGC_EN
//#define Analog_Passthru

int AIC3106_Init()
{
   int i=0;
   int Test_Value;

	// select page 0 and reset codec.
   AIC3106_WriteRegister(AIC3106_REG_PAGESELECT, 0);

   do
   {
	   AIC3106_WriteRegister(AIC3106_REG_RESET, 0x80);
	   for(i=0; i<=100000; i++){};
	   AIC3106_ReadRegister(AIC3106_REG_RESET, ReadVal);
   }
   while(!(ReadVal[0] == 0));

   // config codec regs. please see AIC3106 documentation for explanation. 
   // Document Num: TLV320AIC3106

   

   
	   AIC3106_WriteRegister(3,
				(0 << 7) |	// PLL is disabled
				(4 << 3) |	// PLL Q value = 4
				(2 << 0));	// PLL P value = 2

	   AIC3106_WriteRegister(2,
			(0xA << 4) | 	// ADC fs = fs(ref)/6
			(0xA << 0));	// DAC fs = fs(ref)/6

   


   AIC3106_WriteRegister(7,
   				(0 << 7) |	// fs(ref) = 48kHz (needed only for AGC time constants, not used)
   				(0 << 6) |	// ADC dual rate mode is disabled
   				(0 << 5) |	// DAC dual rate mode is disabled
   				(1 << 3) |	// left DAC datapath plays left channel input data
				(0 << 1) |	// right DAC datapath plays right channel input data
				(0 << 0));	// reserved
   				//0x04);

   AIC3106_WriteRegister(8,
				(1 << 7) |	// BCLK is output (use "1" for output)
				(1 << 6) |	// WCLK is output (use "1" for output)
				(0 << 5) |	// do no place DOUT in high-z when inactive
				(0 << 4) |	// BCLK & WCLK disabled in master mode if code powered down
				(0 << 3) |	// reserved
				(0 << 2) |	// disable 3D effect
				(0 << 0));	// digital mic support disabled
				

   AIC3106_WriteRegister(9,
				(0 << 6) |	// serial data bus in i2s mode
				(0 << 4) |	// audio word length 32 bits//0 - 16bit,3 - 32bits
				(0 << 3) |	// continuous transfer mode
				(0<< 2) |	// don't resync DAC w/ group delay variation
				(0 << 1) |	// don't resync ADC w/ group delay variation
				(0 << 0));	// resync w/o soft muting
				//0x30);	// I2S mode, 32-bit data words, continous xfer mode

   AIC3106_WriteRegister(12,0x00);//filter

							

   AIC3106_WriteRegister(101,
				(0 << 6) |	// read only
				(0 << 5) |	// MFP3 pin as GPI disabled
				(0 << 3) |	// read only
				(0 << 2) |	// MFP2 pin as GPO disabled
				(0 << 1) |	// MFP2 drives low when configured as GPO
				(1 << 0));	// CODEC_CLKIN uses CLKDIV_OUT
				//0x01);

   AIC3106_WriteRegister(102,
				(0 << 6) |	// CLKDIV_IN uses MCLK
				(0 << 4) |	// PLLCLK_IN uses MCLK
				(0 << 0));	// PLL clock divider N = 16
				

   //AIC3106_WriteRegister(10, 0x00);		// data word offset


   AIC3106_WriteRegister(17,0xFF); 	// MIC3L/R not connected to Left ADC
				


   AIC3106_WriteRegister(26,0x80);	
   for(i=0; i<=100000; i++);
   AIC3106_WriteRegister(28,0x8D);	
   for(i=0; i<=100000; i++);
   AIC3106_WriteRegister(27, 0x31);
   for(i=0; i<=100000; i++);
   AIC3106_WriteRegister(34,0xF9);
   for(i=0; i<=100000; i++);
   AIC3106_WriteRegister(103,0x7C);
   for(i=0; i<=100000; i++);
   AIC3106_WriteRegister(104,0x7C);
   for(i=0; i<=100000; i++);

   


   
   AIC3106_WriteRegister(19,
					(0 << 7) |
					(0 << 3) |
					(1 << 2) |// left ADC is powered up(1)
					(3 << 0));//soft stepping disabled

   AIC3106_WriteRegister(20,0xF0); 	// MIC3L/R not connected to Left ADC
   AIC3106_WriteRegister(21,0x78); 	// MIC3L/R not connected to Left ADC

   AIC3106_WriteRegister(22,
					(0 << 7) |
					(0 << 3) |
					(0 << 2) |// right ADC is powered up (1)
					(0 << 0));


   AIC3106_WriteRegister(37,
				(1 << 7) |	// left DAC powered up
				(0 << 6) |	// right DAC powered up
				(2 << 4) |	// HPLCOM configured as independent single-ended output (not used here)
				(0 << 0));	// reserved
				//0xE0);


   AIC3106_WriteRegister(38,
				(0 << 3) |	// HPRCOM configured as differential of HPROUT
				(0 << 2 ) |	// Short circuit protection on all high power output drivers is disabled
				(0 << 1) |	// If short circuit protection enabled, it will limit the maximum current to the load
				(0 << 0));	// reserved
				//0xE0);

   // set the DAC gain   
   AIC3106_WriteRegister(43,
				(0 << 7) |	// left DAC channel is not muted
				(0 << 0));		// left DAC gain setting = 0dB

   AIC3106_WriteRegister(44,
				(1 << 7) |	// right DAC channel is not muted
				(0 << 0));		// left DAC gain setting = 0dB

	#if 0
	// set the DAC gain   
   AIC3106_WriteRegister(43,
				(0 << 7) |	// left DAC channel is not muted
				(0x28 << 0));		// left DAC gain setting = -20dB
				
   AIC3106_WriteRegister(44,
				(0 << 7) |	// right DAC channel is not muted
				(0x28 << 0));		// left DAC gain setting = -20dB

	#endif

#ifdef Analog_Passthru
   /*Start of HPLOUT Output Level Configuration*/
   AIC3106_WriteRegister(46,
				(1 << 7) |	// DAC_L1 is routed to HPLOUT
				(0 << 0));	// DAC_L1 to HPLOUT analog volum control
				//0x80);
#endif
   /*Start of HPLOUT Output Level Configuration*/
   AIC3106_WriteRegister(47,
				(1 << 7) |	// DAC_L1 is routed to HPLOUT
				(0 << 0));	// DAC_L1 to HPLOUT analog volum control
				//0x80);

   AIC3106_WriteRegister(51,
				(0 << 4) |	// HPLOUT output level control = 0dB
				(1 << 3) | 	// HPLOUT is not muted
				(0 << 2) | 	// HPLOUT is weakly driven to a common-mode when powered down
				(0 << 1) |	// read only
				(1 << 0));	// HPLOUT is fully powered up
				// 0x09);
   /*End of HPLOUT Output Level Configuration*/



   /*Start of HPROUT Output Level Configuration*/
   AIC3106_WriteRegister(61,
				(1 << 7) |	// DAC_L1 is routed to HPROUT
				(0 << 0));	// DAC_L1 to HPROUT analog volum control
				//0x80);;

   AIC3106_WriteRegister(65,
				(0 << 4) |	// HPROUT output level control = 0dB
				(1 << 3) | 	// HPROUT is not muted
				(0 << 2) | 	// HPROUT is weakly driven to a common-mode when powered down
				(0 << 1) |	// read only
				(1 << 0));	// HPROUT is fully powered up
				// 0x09);
   /*End of HPROUT Output Level Configuration*/



   /*Start of LEFT_LOP/M Output Level Configuration*/
  AIC3106_WriteRegister(82,
				(1 << 7) |	// DAC_L1 is routed to LEFT_LOP/M
				(0 << 0));	// DAC_L1 to LEFT_LOP/M analog volum control
				//0x80);


   AIC3106_WriteRegister(86,
				(0 << 4) |	// LEFT_LOP/M output level control = 0dB
				(1 << 3) | 	// LEFT_LOP/M is not muted
				(0 << 2) | 	// reserved, read only
				(0 << 1) |	// read only
				(1 << 0));	// read only (must write 1 for some reason)
				// 0x09);
 /*End of LEFT_LOP/M Output Level Configuration*/

   /*Start of RIGHT_LOP/M Output Level Configuration*/
  AIC3106_WriteRegister(89,
				(1 << 7) |	// DAC_L1 is routed to RIGHT_LOP/M
				(0 << 0));	// DAC_L1 to RIGHT_LOP/M analog volum control
				//0x80);

   AIC3106_WriteRegister(93,
				(0 << 4) |	// RIGHT_LOP/M output level control = 0dB
				(1 << 3) | 	// RIGHT_LOP/M is not muted
				(0 << 2) | 	// reserved, read only
				(0 << 1) |	// read only
				(1 << 0));	// read only (must write 1 for some reason)
				// 0x09);
   /*End of RIGHT_LOP/M Output Level Configuration*/



   return SUCCESS;
}



/*###################################################################
#
#			Function Name: AIC3106_WriteRegister
#
#####################################################################
#
#  Arguments	:  Addr, Data
#
#  Description	:  Write register AIC3106 codec chip.
#
#  Return Type	:  int
#
#  Remarks		:  complete
#
###################################################################*/
int AIC3106_WriteRegister(uchar Reg_Addr, uchar Data)
{
	int32 lint32_Rtn = 0, i=0;
	uchar i2c_data[2];

	for (i=0;i<100;i++);
	i2c_data[0] = Reg_Addr;
	i2c_data[1] = Data;

	lint32_Rtn = int32_I2CWrite(I2C0, I2C_AUDIO_CODEC_ADDR, i2c_data, 2, SET_STOP_BIT_AFTER_WRITE);

	return (lint32_Rtn);
}
/*###################################################################
#
#			Function Name: AIC3106_ReadRegister
#
#####################################################################
#
#  Arguments	:  Addr, DataBuff
#
#  Description	:  Read register AIC3106 codec chip.
#
#  Return Type	:  int
#
#  Remarks		:  complete
#
###################################################################*/
int AIC3106_ReadRegister(uchar Reg_Addr, uchar *DataBuff)
{
	int32 lint32_Rtn = 0;

	// write the register address that we want to read.
	lint32_Rtn = int32_I2CWrite(I2C0, I2C_AUDIO_CODEC_ADDR, &Reg_Addr, 1, SKIP_STOP_BIT_AFTER_WRITE);
	if (lint32_Rtn != SUCCESS)
	  return (lint32_Rtn);

	// clock out the register data.
	lint32_Rtn = int32_I2CRead(I2C0, I2C_AUDIO_CODEC_ADDR, DataBuff, 1, SKIP_BUSY_BIT_CHECK);
	return (lint32_Rtn);
}
    TLV_Config.c 
    /*####################################################################################
#
#				File Name: SDRMP_AudioCodec.c
#
#######################################################################################
#
# Project Name	        : SDR-MP
#
# Project Code			:
#
# Created				:
#
# Purpose				: Implementation of LV320AIC3106 functions for OMAP-L138.
#
# Description			:
#
# Author(s)				: Shino Samuel
#
# Version No			:
#
# Revisions				:
#
# Remarks				: Complete
#
# Copyright				: Centre for Development of Advanced Computing(C-DAC), Trivandrum - 2011
#########################################################################################*/
#include "main.h"
#include "SDRMP_McASP.h"
#include "SDRMP_Types.h"
#include "SDRMP_OMAPL138.h"
#include "SDRMP_Global.h"
#include "SDRMP_ISRs.h"
#include "SDRMP_AudioCodec.h"
uchar ReadVal[5] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF};

/*###################################################################
#
#			Function Name: AIC3106_Init
#
#####################################################################
#
#  Arguments	:
#
#  Description	:  Initialise AIC3106 codec chip.
#
#  Return Type	:  int
#
#  Remarks		:  complete
#
###################################################################*/

#define AGC_EN
//#define Analog_Passthru

int AIC3106_Init()
{
   int i=0;
   int Test_Value;

	// select page 0 and reset codec.
   AIC3106_WriteRegister(AIC3106_REG_PAGESELECT, 0);

   do
   {
	   AIC3106_WriteRegister(AIC3106_REG_RESET, 0x80);
	   for(i=0; i<=100000; i++){};
	   AIC3106_ReadRegister(AIC3106_REG_RESET, ReadVal);
   }
   while(!(ReadVal[0] == 0));

   // config codec regs. please see AIC3106 documentation for explanation. 
   // Document Num: TLV320AIC3106

   

   
	   AIC3106_WriteRegister(3,
				(0 << 7) |	// PLL is disabled
				(4 << 3) |	// PLL Q value = 4
				(2 << 0));	// PLL P value = 2

	   AIC3106_WriteRegister(2,
			(0xA << 4) | 	// ADC fs = fs(ref)/6
			(0xA << 0));	// DAC fs = fs(ref)/6

   


   AIC3106_WriteRegister(7,
   				(0 << 7) |	// fs(ref) = 48kHz (needed only for AGC time constants, not used)
   				(0 << 6) |	// ADC dual rate mode is disabled
   				(0 << 5) |	// DAC dual rate mode is disabled
   				(1 << 3) |	// left DAC datapath plays left channel input data
				(0 << 1) |	// right DAC datapath plays right channel input data
				(0 << 0));	// reserved
   				//0x04);

   AIC3106_WriteRegister(8,
				(1 << 7) |	// BCLK is output (use "1" for output)
				(1 << 6) |	// WCLK is output (use "1" for output)
				(0 << 5) |	// do no place DOUT in high-z when inactive
				(0 << 4) |	// BCLK & WCLK disabled in master mode if code powered down
				(0 << 3) |	// reserved
				(0 << 2) |	// disable 3D effect
				(0 << 0));	// digital mic support disabled
				

   AIC3106_WriteRegister(9,
				(0 << 6) |	// serial data bus in i2s mode
				(0 << 4) |	// audio word length 32 bits//0 - 16bit,3 - 32bits
				(0 << 3) |	// continuous transfer mode
				(0<< 2) |	// don't resync DAC w/ group delay variation
				(0 << 1) |	// don't resync ADC w/ group delay variation
				(0 << 0));	// resync w/o soft muting
				//0x30);	// I2S mode, 32-bit data words, continous xfer mode

   AIC3106_WriteRegister(12,0x00);//filter

							

   AIC3106_WriteRegister(101,
				(0 << 6) |	// read only
				(0 << 5) |	// MFP3 pin as GPI disabled
				(0 << 3) |	// read only
				(0 << 2) |	// MFP2 pin as GPO disabled
				(0 << 1) |	// MFP2 drives low when configured as GPO
				(1 << 0));	// CODEC_CLKIN uses CLKDIV_OUT
				//0x01);

   AIC3106_WriteRegister(102,
				(0 << 6) |	// CLKDIV_IN uses MCLK
				(0 << 4) |	// PLLCLK_IN uses MCLK
				(0 << 0));	// PLL clock divider N = 16
				

   //AIC3106_WriteRegister(10, 0x00);		// data word offset


   AIC3106_WriteRegister(17,0xFF); 	// MIC3L/R not connected to Left ADC
				


   AIC3106_WriteRegister(26,0x80);	
   for(i=0; i<=100000; i++);
   AIC3106_WriteRegister(28,0x8D);	
   for(i=0; i<=100000; i++);
   AIC3106_WriteRegister(27, 0x31);
   for(i=0; i<=100000; i++);
   AIC3106_WriteRegister(34,0xF9);
   for(i=0; i<=100000; i++);
   AIC3106_WriteRegister(103,0x7C);
   for(i=0; i<=100000; i++);
   AIC3106_WriteRegister(104,0x7C);
   for(i=0; i<=100000; i++);

   


   
   AIC3106_WriteRegister(19,
					(0 << 7) |
					(0 << 3) |
					(1 << 2) |// left ADC is powered up(1)
					(3 << 0));//soft stepping disabled

   AIC3106_WriteRegister(20,0xF0); 	// MIC3L/R not connected to Left ADC
   AIC3106_WriteRegister(21,0x78); 	// MIC3L/R not connected to Left ADC

   AIC3106_WriteRegister(22,
					(0 << 7) |
					(0 << 3) |
					(0 << 2) |// right ADC is powered up (1)
					(0 << 0));


   AIC3106_WriteRegister(37,
				(1 << 7) |	// left DAC powered up
				(0 << 6) |	// right DAC powered up
				(2 << 4) |	// HPLCOM configured as independent single-ended output (not used here)
				(0 << 0));	// reserved
				//0xE0);


   AIC3106_WriteRegister(38,
				(0 << 3) |	// HPRCOM configured as differential of HPROUT
				(0 << 2 ) |	// Short circuit protection on all high power output drivers is disabled
				(0 << 1) |	// If short circuit protection enabled, it will limit the maximum current to the load
				(0 << 0));	// reserved
				//0xE0);

   // set the DAC gain   
   AIC3106_WriteRegister(43,
				(0 << 7) |	// left DAC channel is not muted
				(0 << 0));		// left DAC gain setting = 0dB

   AIC3106_WriteRegister(44,
				(1 << 7) |	// right DAC channel is not muted
				(0 << 0));		// left DAC gain setting = 0dB

	#if 0
	// set the DAC gain   
   AIC3106_WriteRegister(43,
				(0 << 7) |	// left DAC channel is not muted
				(0x28 << 0));		// left DAC gain setting = -20dB
				
   AIC3106_WriteRegister(44,
				(0 << 7) |	// right DAC channel is not muted
				(0x28 << 0));		// left DAC gain setting = -20dB

	#endif

#ifdef Analog_Passthru
   /*Start of HPLOUT Output Level Configuration*/
   AIC3106_WriteRegister(46,
				(1 << 7) |	// DAC_L1 is routed to HPLOUT
				(0 << 0));	// DAC_L1 to HPLOUT analog volum control
				//0x80);
#endif
   /*Start of HPLOUT Output Level Configuration*/
   AIC3106_WriteRegister(47,
				(1 << 7) |	// DAC_L1 is routed to HPLOUT
				(0 << 0));	// DAC_L1 to HPLOUT analog volum control
				//0x80);

   AIC3106_WriteRegister(51,
				(0 << 4) |	// HPLOUT output level control = 0dB
				(1 << 3) | 	// HPLOUT is not muted
				(0 << 2) | 	// HPLOUT is weakly driven to a common-mode when powered down
				(0 << 1) |	// read only
				(1 << 0));	// HPLOUT is fully powered up
				// 0x09);
   /*End of HPLOUT Output Level Configuration*/



   /*Start of HPROUT Output Level Configuration*/
   AIC3106_WriteRegister(61,
				(1 << 7) |	// DAC_L1 is routed to HPROUT
				(0 << 0));	// DAC_L1 to HPROUT analog volum control
				//0x80);;

   AIC3106_WriteRegister(65,
				(0 << 4) |	// HPROUT output level control = 0dB
				(1 << 3) | 	// HPROUT is not muted
				(0 << 2) | 	// HPROUT is weakly driven to a common-mode when powered down
				(0 << 1) |	// read only
				(1 << 0));	// HPROUT is fully powered up
				// 0x09);
   /*End of HPROUT Output Level Configuration*/



   /*Start of LEFT_LOP/M Output Level Configuration*/
  AIC3106_WriteRegister(82,
				(1 << 7) |	// DAC_L1 is routed to LEFT_LOP/M
				(0 << 0));	// DAC_L1 to LEFT_LOP/M analog volum control
				//0x80);


   AIC3106_WriteRegister(86,
				(0 << 4) |	// LEFT_LOP/M output level control = 0dB
				(1 << 3) | 	// LEFT_LOP/M is not muted
				(0 << 2) | 	// reserved, read only
				(0 << 1) |	// read only
				(1 << 0));	// read only (must write 1 for some reason)
				// 0x09);
 /*End of LEFT_LOP/M Output Level Configuration*/

   /*Start of RIGHT_LOP/M Output Level Configuration*/
  AIC3106_WriteRegister(89,
				(1 << 7) |	// DAC_L1 is routed to RIGHT_LOP/M
				(0 << 0));	// DAC_L1 to RIGHT_LOP/M analog volum control
				//0x80);

   AIC3106_WriteRegister(93,
				(0 << 4) |	// RIGHT_LOP/M output level control = 0dB
				(1 << 3) | 	// RIGHT_LOP/M is not muted
				(0 << 2) | 	// reserved, read only
				(0 << 1) |	// read only
				(1 << 0));	// read only (must write 1 for some reason)
				// 0x09);
   /*End of RIGHT_LOP/M Output Level Configuration*/



   return SUCCESS;
}



/*###################################################################
#
#			Function Name: AIC3106_WriteRegister
#
#####################################################################
#
#  Arguments	:  Addr, Data
#
#  Description	:  Write register AIC3106 codec chip.
#
#  Return Type	:  int
#
#  Remarks		:  complete
#
###################################################################*/
int AIC3106_WriteRegister(uchar Reg_Addr, uchar Data)
{
	int32 lint32_Rtn = 0, i=0;
	uchar i2c_data[2];

	for (i=0;i<100;i++);
	i2c_data[0] = Reg_Addr;
	i2c_data[1] = Data;

	lint32_Rtn = int32_I2CWrite(I2C0, I2C_AUDIO_CODEC_ADDR, i2c_data, 2, SET_STOP_BIT_AFTER_WRITE);

	return (lint32_Rtn);
}
/*###################################################################
#
#			Function Name: AIC3106_ReadRegister
#
#####################################################################
#
#  Arguments	:  Addr, DataBuff
#
#  Description	:  Read register AIC3106 codec chip.
#
#  Return Type	:  int
#
#  Remarks		:  complete
#
###################################################################*/
int AIC3106_ReadRegister(uchar Reg_Addr, uchar *DataBuff)
{
	int32 lint32_Rtn = 0;

	// write the register address that we want to read.
	lint32_Rtn = int32_I2CWrite(I2C0, I2C_AUDIO_CODEC_ADDR, &Reg_Addr, 1, SKIP_STOP_BIT_AFTER_WRITE);
	if (lint32_Rtn != SUCCESS)
	  return (lint32_Rtn);

	// clock out the register data.
	lint32_Rtn = int32_I2CRead(I2C0, I2C_AUDIO_CODEC_ADDR, DataBuff, 1, SKIP_BUSY_BIT_CHECK);
	return (lint32_Rtn);
}

  • 0 in reply to Sreelakshmi Radhakrishnan
    TI__Guru* 84915 points
    Hi, Sreelakshmi,

    This issue could be related with the maximum gain allowed. Could you increase the maximum gain to ensure that the expected signal can be reached without problems? Also, could you program the faster attack and decay times?

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 330 points

    Heloo Luis,

    Thanks for the reply. As part of testing, we are providing sufficiently high input level (1Vpp), set AGC target level to -5.5dB with refernce to the full scale value and the gain much higher than required (6dB). In this case also we are seeing the out put to vary between 521.4mVrms to 493.2Vrms. We are observing this in codec loopback test mentioned earlier.  Can you Please comment us on this

    Thanks

    Rejeesh S Raj