Hi,
I'm using the TLV320AIC3254. On the eval board everything runs properly. On our first prototype there might be a problem with powering up the analog blocks.
There is a differential signal on IN3L and IN3R routed to the Left PGA. The input level is in the range from 100uVRMS up to 3mVRMS. With the AGC function the output signal has a level of about 5mVRMS. The same setting as on the eval board is not running...
IOVDD and LDOIN are supplied by 3.3VDC. I use the internal LDOs for generating AVDD and DVDD. LDOselect is connected with 4k7ohm to 3.3VDC. Below is my power-up sequence.
##################################
# Software Reset and Power Configuration
##################################
# Software Reset
w 30 00 00
w 30 01 01
# Power Configuration Register
w 30 00 01
w 30 01 08
# LDO Control Register, DVDD, AVDD = 1,77V, Enable Analog Blocks, Power-up AVDD LDO
w 30 02 A1
# Analog Input Quick Charging Config Reg. (Register 71) (Analog input power up time, 6.4ms)
w 30 47 32
# Reference Power-up Config Reg. (Register 123) (Setup time 120ms after analog blocks)
w 30 7B 03
# Common Mode Control, HPL powered with LDOIN, LDOIN input range=1,8V...3,6V
w 30 00 01
w 30 0A 03
If I route for testing IN1L to HPL (page 1/ register 12 / value 0x04), I'm getting a signal with 600uVRMS (Input 3mVRMS). The signal is very "dirty". I use an audio analyzer. It's like pulsating. Can anyone "open my eyes"?
Thanx Alessandro