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Power up analog blocks with TLV320AIC3254

Other Parts Discussed in Thread: TLV320AIC3254, PUREPATHSTUDIO, INA129

Hi,

I'm using the TLV320AIC3254. On the eval board everything runs properly. On our first prototype there might be a problem with powering up the analog blocks.

There is a differential signal on IN3L and IN3R routed to the Left PGA. The input level is in the range from 100uVRMS up to 3mVRMS. With the AGC function the output signal has a level of about 5mVRMS. The same setting as on the eval board is not running...

IOVDD and LDOIN are supplied by 3.3VDC. I use the internal LDOs for generating AVDD and DVDD. LDOselect is connected with 4k7ohm to 3.3VDC. Below is my power-up sequence.

##################################
# Software Reset and Power Configuration
##################################
#  Software Reset
w 30 00 00
w 30 01 01
#  Power Configuration Register
w 30 00 01
w 30 01 08
# LDO Control Register, DVDD, AVDD = 1,77V, Enable Analog Blocks, Power-up AVDD LDO
w 30 02 A1
# Analog Input Quick Charging Config Reg. (Register 71) (Analog input power up time, 6.4ms)
w 30 47 32
# Reference Power-up Config Reg. (Register 123) (Setup time 120ms after analog blocks)
w 30 7B 03
# Common Mode Control, HPL powered with LDOIN, LDOIN input range=1,8V...3,6V
w 30 00 01
w 30 0A 03


If I route for testing IN1L to HPL (page 1/ register 12 / value 0x04), I'm getting a signal with 600uVRMS (Input 3mVRMS). The signal is very "dirty". I use an audio analyzer. It's like pulsating. Can anyone "open my eyes"?

Thanx Alessandro

  • Hi, Alessandro,

    The power configuration seems to be in order. If my understanding is correct, in the EVM your configuration is working properly, but in your design it seems to be a problem. Could you provide your entire register configuration, please? Additionally, could you provide a schematic to review all the connections?

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,

    thank you for the fast reply. Your understanding is correct.

    You find my entire code below. For Information: we are using SPI (not I2C) as control interface to MSP430. That's working fine, we can write registers and readout them. The MCLK has 11,2896MHz. We applied some EMI filters, but they are working fine with the Eval board.

    The signal routing should be IN3L and IN3R (differential signal) => Left MICPGA => AGC functionality=> MAL => HPL (single ended)

    ###############################################################################################
    # Software Reset and Power Configuration
    ###############################################################################################
    # select page 0, Register 1, Software Reset
    w 30 00 00
    w 30 01 01
    # select page 1, Register 1, Power Configuration Register
    w 30 00 01
    w 30 01 08
    # LDO Control Register, DVDD, AVDD = 1,77V, Power-up AVDD LDO
    w 30 02 A1
    # Analog Input Quick Charging Config Reg. (Register 71) (Analog input power up time, 6.4ms)
    w 30 47 32
    # Reference Power-up Config Reg. (Register 123) (Setup time 120ms after analog blocks)
    w 30 7B 03
    # Common Mode Control, HPL powered with LDOIN, LDOIN input range=1,8V...3,6V
    w 30 00 01
    w 30 0A 03
    ###############################################################################################
    # OSR and Clock Settings
    ###############################################################################################
    # select page 0, Register 4 Clock Setting Register, MCLK = PLL Input Clock
    w 30 00 00
    W 30 04 00
    # DAC OSR (oversampling Ratio) Setting Register 1 MSB value (Register 13) DOSR = 1024
    w 30 0D 00
    # DAC OSR Setting Register 2, LSB value (Register 14) DOSR = Reset Value
    w 30 0E 80
    # Clock Setting Register 8 (Register 18) NDAC = 1
    w 30 12 81
    # Clock Setting Register 9 (Register 19) MDAC = 2
    w 30 13 82
    # Clock Setting Register 6 (Register 11) NDAC = 1
    w 30 0B 81
    # Clock Setting Register 7 (Register 12) MDAC = 2
    w 30 0C 82
    ###############################################################################################
    # Audio Interface Setting
    ###############################################################################################
    w 30 00 00
    # BCLK/WCLK input, I2S: 0x00, LJF: 0xC0
    w 30 1B 00
    # Loopback control, Audio Data is routed to Audio Data out
    w 30 1D 20
    # GPIO setting
    w 30 34 00
    # DOUT Control (DOUT is Primary DOUT)
    w 30 35 12
    # DIN Control (DINT is Primary DIN)
    w 30 36 04
    ###############################################################################################
    # SPI Interface Setting
    ###############################################################################################
    w 30 00 00
    # MISO Control, data output for SPI interface, I2C disabled
    w 30 37 02
    # SCLK Control, SPI clock
    w 30 38 02
    ###############################################################################################
    # Input Routing
    ###############################################################################################
    w 30 00 01
    # Left MICPGA Positive Terminal Input Routing Config Reg (Register 52) IN3L
    w 30 34 04
    # Left MICPGA Negative Terminal Input Routing Config Reg (Register 54) IN3R
    w 30 36 04
    # Left MICPGA Volume control Register (Register 59) 47.5dB
    w 30 3B 5F
    ###############################################################################################
    # ADC Setup
    ###############################################################################################
    # select page 0, ADC Channel Setup Register (power up LADC, un-mute LADC)
    w 30 00 00
    w 30 51 80 08
    # Left Channel ADC Volume Control Register 0dB
    w 30 53 00
    # ADC Power Tune Configuration (PTM_R4 = high performance)
    w 30 00 01
    w 30 3D 00
    ###############################################################################################
    # AGC Setup
    ###############################################################################################
    w 30 00 00
    # AGC Noise Threshold -30dB
    w 30 57 82
    # AGC Max Gain (0x46=35dB, 0x50=40dB, 0x70=56dB)
    w 30 58 46
    # AGC Attack Time
    w 30 59 50
    # AGC Decay Time (0x00 = 512 ADC Word Clocks)
    w 30 5A 00
    # Noise  Debounce Time (0x0C = 2*4096 ADC Word Clocks)
    w 30 5B 0C
    # Signal Debounce Time (0x03 = 8 ADC Word Clocks)
    w 30 5C 03
    # Left Channel AGC Control Register 1 (Register 86)
    # AGC Target Gain -24.0dBFS, Gain hysteresis +/-1.5dB
    w 30 56 F3
    ###############################################################################################
    # Output Routing
    ###############################################################################################
    # Register 12, HPL Routing Register (0x02 MAL=>HPL)
    w 30 00 01
    w 30 0C 02
    # power up MAL and HPL
    w 30 09 22
    # Mixer Amplifier Left (MAL) Volume Control Register -12dB
    w 30 18 19
    # unmute HPL, PGA Gain -6dB
    w 30 10 3A

  • Hi Luis,

    here is a part of the schematic:

    Yesterday I was able to route IN1L directly to HPL. I had half signal amplitude (even though of 0dB) at the output. So power up is really working correct.

    Best regards

    Alessandro

  • Hi, Alessandro,

    You're right. I tested your script in the EVM and it works correctly. So, I think that it must be a connection problem. I compared your schematic with the EVM and it could be related with the input capacitors. Have you tried placing a 0.47uF capacitor in the input as the following picture shows:

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi Luis,

    you are good! Problem solved! Output is now running.

    What is the explanation? The inline capacitors make galvanic insulation between input signal and measured output signal. Though the audio analyzer has differential inputs/outputs, it connects the ground potentials in a way.


    I will try to replace the inline capacitors by an audio transformer. Maybe the audio transformer provides the same effect (galvanic insulation).

    Thank you very much.

    Best Regards, Alessandro

  • Hi, Alessandro,

    I'm glad to read that the problem was solved. The input capacitors are used to avoid the negative values at the analog input. They add a DC level at the inputs. It can be measured on the analog inputs.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,

    I have a problem with the AGC function. It is not working. The same configuration on the eval board is working fine. For example inputs 0,1mV...50mV generate an output of 15mV. On the eval board I'm able to change the target level, max AGC gain and so on with a result at the output.

    On my prototype only the Left MicPGA, MAL and HPL are working and gererating an amplification. AGC is not working. I can switch of the Left ADC and have no change at the output. Also changing the target level or max AGC gain shows no change at the output.

    If I compare the ADC Flag Register (page 0, reg. 0x24) the eval board provides a 0x68, the prototype 0x48. Where could be the problem? Is there a problem with generating AVDD/DVDD? I have checked the clock settings and the master clock of both boards, they are identically.

    The code is almost the same as above. The input routing of IN3 is done with 40k. I have one prototype with input-inline-capacitors and one with audio transformer. Both show the same behavior.

    Thank you and Best regards, Alessandro

  • Hi, Alessandro,

    Have you tried enabling the digital loopback (page 0, register 29, D4) instead the MAL to HPL connection? It routes the ADC output to the DAC input. So, it will ensure that the AGC is on the signal path.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,


    it is still not working. I have configured the DAC as supposed in the Design and Configuration Guide, Appendix E. There is no output signal. I have replaced the codec (with the hope it has a damage) but with no success.

    Switching off and on the ADC doesn't change the output signal.

    I have changed the output capacitors into 47uF. The capacitors between DVDD and AVDD to GND are changed into 22uF. Both actions had no influence on the output signal. The circuit is now completly identical to the eval board.

    I have observed the power up with oscilloscope. The reset-pin is pulled high after 1 second. The supply voltages (AVDD, DVDD, LDOin) are stable.


    If you have any further ideas, please let me know.

    Best regards, Alessandro

  • Hi, Alessandro,

    Have you disabled the noise threshold? The signal seems to be too small and probably it is getting affected by this function.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,


    I have disabled the noise threshold with no succes to my problem. I amplify the input signal with 47.5dB with the Left MicPGA. The input signal should be high enough for the ADC/ADC noise threshold?!

    Maybe there is a problem with the HPVDD and IOVDD. On my prototype these two supplies are connectec and supplied by one LDO (TPS7150). On the Eval board there are two separate supplies. If I disconnect W18 and connect TP31 to W16, the target level is not reached. So there is a degradation on the eval board as well.

    What is the maximum allowed input voltage for the ADC, if I have configured Power Tune Mode 4 with full chip common-mode 0,9V? (refer to slaa404c, page 11).

    If you have any idea, please let me know. Thank you very much.

    Best regards, Alessandro

  • Hi, Alessandro,

    Could you try to power the IOVDD and HPVDD pins with two separate supplies, please? It seems to be the only difference between your prototype and the eval board.

    Regarding your question about the maximum input voltage, the analog input range is -0.3V to AVdd + 0.3V. It is suggested not to reach these limits because they may cause permanent damage to the device.

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi, Alessandro,

    I will answer the questions on this E2E thread in order to accumulate all the information about this issue.

    1. Concerning the ADC input: the ADC is in block diagram after the MicPGA, what is the maximum input for ADC? If I apply a voltage of 3mV (for example to IN3L/R) and MicPGA Gain is 20dB the input of the ADC would be 30mV. That is more than the typical preferred 10mV in the datasheet:

    The Audio ADC configured in single-ended input has a typical input signal level of 0.5 Vrms. When the codecs are configured in differential mode, the typical input signal level can reach the double of the input signal level in single-ended mode. This means that the real typical value must be 1Vrms. There should be a typo error on this datasheet.

    Regarding your question about the maximum input for the ADC, you may take a look of the following picture:

    The ADC works from 0V to AVDD. If these limits are not respected, it could be a saturation problem at the output. So, we recommend to work between these values.

    2. Where is the AGC gain induced? Is it the MicPGA? The MicPGA has a gain range from 0…47,5dB, the AGC gain range is from 0…53,5dB Can you explain the relation between MicPGA and AGC gain effected on MicPGA?

    As opposed to manually setting the PGA gain, in the AGC mode, the circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very weak. This means that the PGA gain configuration is ignored when the AGC is enabled. It actually accepts higher gains such 58dB. So, the only differences would be the gain limit and the PGA control.

     

    3. I have an input signal on IN3L and IN3R with 10mVrms. If I measure between TP6 and TP7 (evalboard) the IC turns into reset. I use an Rohde&Schwarz Audio analyzer in differentiell mode. The inputs seem to be very sensitive.

    There are 2 ways which can produce a reset on the codecs: hardware reset, software reset (which can be acceded only by register configuration). However, there could be another situations that could induce a reset on the codecs. These situations are related with a unexpected condition on the codec connection. If the power supplies are not well regulated, the codec could turn into a reset mode. Additionally, the codec has internal protection against over-current or short-circuit which can produce a reset when this problems appears. I don't have information about how the Audio analyzer works. However, it could be producing reset by one of these reasons. 

     

    I will continue doing more tests to accelerate the solution of this problem. So, I will check again your configuration on the EVM and I will review your schematic with my colleagues to have another point of view.

    Please let me know if I omitted an information or test to do. Additionally, if you have more questions or comments, please let me know.

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi, Alessandro,

    We reviewed again your schematic and all seem to be in order. We didn't observe wrong connections. However, I continued with the tests on the EVM. I tried to find a way to cause a bad AGC behavior. It seems that the AGC is strongly related with the MCLK function. When the MCLK is not working when the codec is configured, the AGC doesn't work. Have you checked the MCLK on your board? Is it applied correctly?

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi Luis,


    Thanks for your fast reply.

    The MCLK on the prototype seems to be ok.

    If I measure the MCLK for a while the mean frequency is 11.2896MHz.

    For comparsion I did the same with the EVM. Compare to the picture below.

    The clock on the prototype should be in the valid range.

    We did the configuration / loading of the configuration as follows: Power up => Codec is for 5 seconds in hardware reset => 5 seconds for default configuration => loading the configuration from the host processor (with software reset at the beginning). AGC is still not working.


    For completion: I did supply IOVDD and HPVDD with to different supplies. There was no positive effect to the problem.
    According the reset problem: the reset pin is still high, when going into reset. So maybe overcurrent/overload is the reason for the reset.

    Best regards, Alessandro

  • Hi Luis,

    Thanks for your fast reply.

    The MCLK on the prototype seems to be ok.

    If I measure the MCLK for a while the mean frequency is 11.2896MHz.

    For comparsion I did the same with the EVM. Compare to the picture below.

    The clock on the prototype should be in the valid range.

    We did the configuration / loading of the configuration as follows: Power up => Codec is for 5 seconds in hardware reset => 5 seconds for default configuration => loading the configuration from the host processor (with software reset at the beginning). AGC is still not working.

    For completion: I did supply IOVDD and HPVDD with to different supplies. There was no positive effect to the problem.

    According the reset problem: the reset pin is still high, when going into reset. So maybe overcurrent/overload is the reason for the reset.

    Best regards, Alessandro

  • Hi, Alessandro,

    It's weird that the AGC is still not working after all these tests. It should work similar as the EVM. Have you tried to use the programmable miniDSP of the TLV320AIC3254? This miniDSP includes algorithms such filters, gains, mixers and AGC. It can be programmed by PurePath Studio. Is there any problem if you include the programmable miniDSP in your application?

    AGC.pdf

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi Luis,


    I've registered for PurePath Studio. I haven't yet a download...

    I did some more measurements to the MCLK:

    I applied the clock from the EVM to our prototype (with complete configuring via SPI from EVM). For a further test I applied a external clock from a frequency generator. Even not appliying a MCLK provides the same result (linear amplification, no AGC).

    I observed the jitter as mentioned in the pictures below:

    This is the prototype. Please look at measurement P5. The jitter mean value is 1,94ps.

    This is the EVM. Please look at measurement P5. The jitter mean value is 3,6ps.

    We use a programmable oscillator from discera (with internal PLL). I will try to use a fixed output oscillator tomorrow (maybe it is more proper).

    We talked about this table below. Do you have any awareness?

    If I configure Rin as 10kOhms and have a differential signal, I receive the gain from the first colum.

    Thanks so far

    Best regards, Alessandro

  • Hi Luis,

    I have done some more tests.

    I powered the AVDD and DVDD from external power supply. That had no consequence to my problem. I have disassembled the resistor at LDOinSelect (pulled that pin to GND) and changed the configuration (switched off internal LDO).

    For another test I had a look at page 1 Register 0x02: If I power up/down the AVDD LDO (Bit D0 1<=>0) the output on/off. If I change Bit D3 there is no reaction. My understanding was, when disabling the analog blocks all amplifieres (MicPGA, MAL, HPL) and the ADC/AGC turn off. I didn't yet test this on the EVM.

    I've installed Pure Path Studio, so I can start tomorrow with programming. Are there any examples available?

    Best regards, Alessandro

  • Hi, Alessandro,

    It should work with the MCLK characteristic that you provided even if the jitter value changes. Regarding the analog PGA versus input configuration table, did you obtained this gain on the EVM too? Or is it a prototype's problem?

    Regarding your question about PurePath Studio, please take a look of the following wiki article: https://e2e.ti.com/support/data_converters/audio_converters/w/design_notes/3320.getting-started-on-purepath-studio. This video explains how to use PurePath Studio. I will guide you step-by-step if it is necessary.

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi Luis,

    Concerning the analog PGA versus input configuration table:

    Configuration: 10kOhm inline-resistors => results in 0dB with LeftMicPGA 0dB (0x3B 0x00), MAL 0dB (0x10, 0x00), HPL 0dB (0x18 0x00). According to tabe 2.4 in the RefGuide it should be 6dB in differential mode.

    The yellow rows show saturation. Can you reproduce that behavior? Is that a fault in the RefGuide?


    PurePathStudio doesnt find the EVM and there are no frameworks for AIC3254 available. I have seen in another e2e-thread that there might be a wrong firmware. The installed firmware is V3.04. Is that correct? Or where do I get the right one?


    Best regards, Alessandro

  • Hi, Alessandro,

    I suspect that it could be related with the input voltage range and the AGC could be related with this too. The typical input voltage on this device is 0.5 Vrms for single ended input and 1Vrms for differential. When the input signal is near of these values, the gain is similar to the expected one.

    I made some tests with the 10k resistor and differential configuration. In the most of cases, the expected gain is 6.0 dB. However, when the input voltage approached to the 5mVrms that you applied, the obtained gain was different.

    Input Voltage (mVrms) Observed gain (db)
    500 5.6 dB
    300 5.6 dB
    100 5.08 dB
    50 4.5 dB
    10 1.58 dB
    5 0.5 dB

    I suspect that the codec is not working correctly due to the input voltage. Is it possible to try with higher voltage in your application? Does this improve the AGC function?

    Regarding your question about PurePath Studio, probably there is no framework for AIC3254 available because you are using the Home version. Did you check if your version is the Portable version? The Portable version is used for this kind of codecs.

    I hope this helps you. Please let me know if you still have questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi Luis,

    I did some measurements. I can't observe your measured gain. I got the following values:

    The three boards behave very similiar. The RefGuide says on its page 8 IN3_L and IN3_R means differential input. Is my understanding correct?

    For my application we want to use a microphone with input values from 0,1mV to 3mV (typical). Are there passive microphones which apply higher voltages (regarding the typical input voltage of 1VoltRMS)?


    PurePathStudio:

    I've installed the portable version and upgraded the firmware again to V3.04. I now have the right frameworks. But it's not possible to download the "code". I receive the following error message:

    It says it has found a board, but cannot download the application. Could you please give me an advice?

    Best regards, Alessandro

  • Hi, Alessandro,

    I used the IN2_L and IN2_R inputs for these tests. I placed all the gains to 0dB and used the 10k resistor. I calculated the gain as 20*log(Vout/IN2_L). Is this the same procedure that you applied?

    Regarding your question about the passive microphones voltages, is it possible to pre-amplify the signal before the codec?

    Finally, could you provide the application that you made on PurePath Studio? If the EVM is recognized with the AIC3254CS software, PurePath Studio should recognize it too. Could you give more details of your application, please?

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,

    I used the IN3_L and IN3_R inputs, but there should be now difference. My calculation is same as yours. Anywhere this is not consistent...

    Concerning a pre-amplification: We selected this IC, because it seemed the chip is able to work with this levels. The EVM is able to work with the small input levels, so there should be a way that the prototype works too. Our design has to be very small, so we prefer a solution without pre-amplifier. If there is no other solution, we have to assemble a pre-amplifier.

    PPS is now working. I've made a programm with simple ADC to DAC, AGC block and Volume control. This is working on the EVM with small/big levels (1mV/1000mV) very well. If I try to configure the prototype (still connected to the SPI-interface of the EVM) with PPS I receive an error message (compare to the picture below). This message occurs if I change the value of the volume control. There is now audio at the output. There is the same problem as on the analog path (ADC or any digital component seems to be not running). Is there a test to control if the miniDSP/ADC/DAC is working correct?

    If I modify the program (deletion of AGC and Volume control block), there is still no audio output.

    I made a test of AVDD. During configuration the level slowly decreases, then drops suddenly to almost zero (200mV) and rises up again. I observed a smilar behavior with the EVM. Is that normal? The other supply voltages (DVDD, IOVDD, HPVDD) stay stable.

    Best regards, Alessandro

  • Hi, Alessandro,

    It's strange that you're getting different results from other inputs. This is not normal. I agree with you, the prototype should work as the EVM. Additionally, they have similar connections, so the measurements should be the same.

    Regarding your message error, I made some tests on the EVM. It seems that this message appears when the clocks are not being applied to the codec. When I enabled the clocks on the MODEVM-INTERFACE BOARD, the message didn't appear. Could you check the clocks connections, please?

    Regarding the AVDD test, I repeated the configuration several times, but it seems that the AVDD voltage doesn't change. I didn't observe your results. Could you describe the moment when it happens? Is it when you download the code to the EVM?

    Finally, I don't know why the prototype is not similar to the EVM in certain cases. Have you considered that the codec could be damaged? Have you tried to replace it?

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,

    some test I later, I report:

    I did the test with the "PGA vs Input configuration" on IN2L and IN2R and received the same result as before. If I apply 0dB and 10kOhms, I still receive 0dB (It should 6dB...)

    The prototype doesnt run with PPS. The MCLK is correct during the whole time (I can measure it at the pin/test point). Is there a more simple test as routing Input to ADC, ADC to DAC and DAC to output? What have you meant with clock connection?

    AVDD tests: AVDD only chrashes with PPS. If I load a setting with the Control Software, AVDD stays stable (in both cases, EVM and prototype). It is difficult to describe the moment, but look to the following plot. This is on the prototype, the EVM is almost the same. The yellow line is SCLK from the SPI interface and the green line is the AVDD.

    We have replaced the codec several times. Today we assembled the standard catalogue variant, but there was the same behavior as with the automotive variante. So I exclude a damage.

    Best regards, Alessandro

  • Hi, Alessandro,

    I apologize for the late response.

    I noticed that you made your last test with IN2L and IN2R. In the previous post, you commented that the IN3L and IN3R lines could be used to get the similar results. Is it possible to make some tests with IN3L and IN3R lines to ensure that the AGC is not working correctly? I suspect that this problem could be related with the analog inputs.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,

    I have already done the tests with IN3. IN3 behaves same as IN2. There is no difference. Both inputs don't behave like explained in the datasheet.

    Could you specify the valid input for AGC. I use a instrumentation amplifier as pre-amplifier (Texas Instruments: INA129). My test shows as result that the input range is from 3,5mV up to 1V in single ended configuration. This is another inconsistent point in the datasheet. It says 0,5Vrms in single ended and 1Vrms in differential mode.

    It is still not clear why the AGC is not working in differential mode. In single ended mode with pre-amplifier AGC is now working, but the input range is two small for our application. I still would appreciate the behavior of the EVM.

    Best regards, Alessandro

  • Hi Luis,

    Edit to my post above: AGC isn't working with Pre-amplifier..... Concerning some invidous settings, it seemed that AGC is working. The valid input range is in single ended up to 500mVrms. In the single ended configuration with pre-amplifier I use the IN1L and CM1L. That means another input as in differential and it doesn't work either. So I will wait for your answer.

    Thanks, Best regards, Alessandro

  • Hi, Alessandro,

    I made several tests with the EVM. I tested the following code in order to use IN3L and IN3R as differential inputs.

    3582.Script.txt
    # Page 0
    w 30 00 00
    # Software reset
    w 30 01 01
    # Page 1
    w 30 00 01
    # Disable weak connection of AVDD with DVDD
    w 30 01 08
    # Analog blocks enabled
    w 30 02 00
    # Analog inputs power up time is 6.4ms
    w 30 47 32
    # Reference will power up in 40ms
    w 30 7B 01
    # Page 0
    w 30 00 00
    # DOSR = 128
    w 30 0D 00
    w 30 0E 80
    # NADC = 1
    w 30 12 81
    # MADC = 2
    w 30 13 82
    # NDAC = 1
    w 30 0B 81
    # MDAC = 2
    w 30 0C 82
    # Page 1
    w 30 00 01
    # MICBIAS on
    w 30 33 78
    # IN3L to Left MICPGA with 10k
    w 30 34 04
    # IN3R to Left MICPGA with 10k
    w 30 36 04
    # Left/Right MICPGA gain is enabled
    w 30 3B 00 00
    # Page 0
    w 30 00 00
    # Left/Right ADC channel powered up / un-muted
    w 30 51 C0 00
    # Page 0
    w 30 00 00
    # AGC settings
    w 30 57 80 74 50 00 0C 03
    # AGC enabled
    w 30 56 82
    # Digital loopback
    w 30 1D 10
    # Left DAC enabled
    w 30 3F 94
    # DAC un-muted
    w 30 40 04
    # Page 1
    w 30 00 01
    # LDAC to LOL
    w 30 0E 08
    # LOL un-muted
    w 30 12 00
    # LOL powered on
    w 30 09 08
    

    This test was made with the internal LDOs and with the external AVDD and DVDD. In both cases, I obtained a constant output on LOL output. It seems that the AGC is working correctly with an input signal from 10mV to 1.3V.

    Could you verify if this configuration (or a similar configuration) works correctly?

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi Luis,


    I've tested your script above. I've modified some lines (e.g. output is HPL)

    .

    script_modified.txt
    i spi8
    # Page 0
    w 30 00 00
    # Software reset
    w 30 01 01
    # Page 1
    w 30 00 01
    # Disable weak connection of AVDD with DVDD
    w 30 01 08
    ### Analog blocks enabled
    w 30 02 A1
    # Analog inputs power up time is 6.4ms
    w 30 47 32
    # Reference will power up in 40ms
    w 30 7B 01
    # Common Mode Control, HPL powered with LDOIN, LDOIN input range=1,8V...3,6V, CM=0.9V
    # CM-HPL = 1,5V
    w 30 00 01
    w 30 0A 53
    # Page 0
    w 30 00 00
    # DOSR = 128
    w 30 0D 00
    w 30 0E 80
    # NADC = 1
    w 30 12 81
    # MADC = 2
    w 30 13 82
    # NDAC = 1
    w 30 0B 81
    # MDAC = 2
    w 30 0C 82
    # Page 1
    w 30 00 01
    # MICBIAS on
    #w 30 33 78
    # IN3L to Left MICPGA with 10k
    w 30 34 04
    # IN3R to Left MICPGA with 10k
    w 30 36 04
    # Left MICPGA gain is enabled
    w 30 3B 00
    # Page 0
    w 30 00 00
    # Left/Right ADC channel powered up / un-muted
    w 30 51 C0 00
    # Page 0
    w 30 00 00
    # AGC settings
    w 30 57 80 74 50 00 0C 03
    # AGC enabled
    w 30 56 82
    # Digital loopback
    w 30 1D 10
    # Left DAC enabled
    w 30 3F 94
    # DAC un-muted
    w 30 40 04
    # Page 1
    w 30 00 01
    # LDAC to HPL
    w 30 0C 08
    # HPL un-muted
    w 30 10 00
    # HPL powered on
    w 30 09 10

    I used the new (unmodified) EVM. But I received no output. The DAC is not working. If I delete the DAC/digital loopback section and insert the output routing to MAL and HPL I receive an output signal. The configuration (power, clock setting, input routing) seems to be ok. I tested the configuration with HPL and LOL as output.

    Can you find a mistake in my configuration?

    Thank you, Best regards, Alessandro

  • Hi, Alessandro,

    It seems that the left headphone output is not powered up. The last command line must be w 30 09 20 in order to power up HPL instead HPR. Could you try with this, please?

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,

    I changed the last command line. I receive an output signal with your code on the EVM.

    Here is my actual issue list with things, not working on the prototype:

    • AGC function (analoge blocks/amplifiers MAL, HPL are working, but no AGC by LeftMicPGA)
    • configuring with PurePathStudio (digital components, AGC, Filtering, Volume Control...)
    • differential input (is working)

    We use small input levels (0,1mV up to 15mV). The EVM is working with these levels. The output level shall be 10mV or 15mV, but never exceed 30mV. If it is necessary we can amplify the input signal.

    In parallel to these issues, I'm evaluating noise cancellation, gate function, etc. on the EVM.

    Best regards, Alessandro

  • Hi Luis,


    I have a new question. We applied to our prototype and the EVM the same configuration/settings. We compared every pin. On the EVM is applied a BCLK (2,82MHz) and WCLK (44,1kHz). On our prototype we don't apply these clocks, when not using the I2S interface. We want to hold the I2S ready for future use (I2S output).

    For test only, we diassembled the resistors R21 and R22 on the EVM. With floating BCLK and WCLK pins the AGC on the EVM doesn't work. The behavior is the same as on out prototype.

    We generate the WCLK from the BCLK with a 5-bit counter (as mentioned in a anotation note from TI). The MSP430 provides the BCLK. For test we have a command which generates only two WCLK-clocks.
    If we set up the prototype for AGC, it is not working. After applying two WCLK-clocks and correspondent BCLK-clocks, the AGC is running!!

    What has to be applied to the WCLK and BCLK pins during start-up? Is there maybe a register which has to be configured, if not using I2S?

    Best regards, Alessandro

  • Hi, Alessandro,

    I had a similar situation with the TLV320AIC3254 beep generator block. This block cannot work until several BCLK and WCLK pulses are sent to the codec. This is related with the DAC processing blocks. They must be initialized by these pulses for the correct behavior. After the initialization takes place, the beep generator worked as expected.

    So, this should be a similar situation but on the ADC side. The ADC processing blocks must be initialized in order to use the AGC block.

    Regarding the registers to be configured, in case of a slave configuration, it would be necessary to wait for the BCLK and WCLK pulses until the initialization is made. In case of master configuration, there's a register that can be used to generate the BCLK/WCLK pulses even if the ADC/DAC is disabled. Page 0 / Register 29 / Bit D2 generates the BCLK/WCLK when the codec is powered down.

    So, was this issue solved after enable the I2S clocks?

    Best regards,
    Luis Fernando Rodríguez S.

  • Hi, Luis,

    we are still measuring on the issue with the BCLK/WCLK. I will report our results.

    Another question concerning the ADC/AGC:

    Pin 18 is the Vref pin. What is the Vref voltage exactly for?  The Reference Guide describes the reference voltage on page 82. It says all data converters (I expect also ADC) uses the Vref as internal voltage. You sent the picture below. What uses the ADC the Vref voltage for and what for the AVDD voltage?

    Second question would be how is AGC working? I will concrete my question: Description of AGC is in the Refernce Guide on page 17. There is written:

    "The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal."

    What is meant with absolute average? The sample rate is much more higher than the signal frequency. So during zero crossing the absolute value of the signal will always be smaller than the nominal amplitude of the output signal. How is the ADC sampling the input signal and how is the ADC signal processor deciding if the signal is below/over the target level? We try to find a convenient setting for the AGC parameters. Therefore it would be good to understand this situation.

    Best regard, Alessandro

  • Hi, Alessandro,

    Regarding your question about the Vref voltage, I will try to explain it with the help of a register: Page 1 / Register 10 Common Mode Control Register. Specifically, Bit D6 is used to modify the Full Chip Common Mode (0.75V or 0.9V). We can see this voltage at the analog inputs and outputs when they are being used. So, the REF pin is actually the output of the band-gap circuit which generates this reference voltage. Actually, if you modify the bit D6, you may see a change on the REF pin (such the analog inputs and outputs). This pin requires a capacitor for decoupling the reference voltage. By other hand, the AVDD voltage is used as reference for the digital output/input as described on the picture above.

    Regarding your question about the AGC, the AGC must maintain nominally constant the output voltage at the output of the PGA. So, to reach this objective, the AGC block must calculate an average of the signal. Once the average is calculated, the AGC algorithm can determine if the PGA level must be reduced or increased in order to get the average of the signal.

    Part of the AGC is performed in hardware and part of it in software as part of the decimator. This means that the processing engine needs to run for the AGC to work. So, that's why the AGC needs the BCLK/WCLK to work.

    I hope this helps you. Please let me know if you have more questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.