AIC3106 sampling rate 96 kHz

Sherry Ismail

The codec AIC3106 on board of LCDKC6748 works fine for 48 kHz. How do I switch on 96kHz ?

My setup:

Codec = slave mode ,
DSP McASP module = Master mode providing BCLK, WCLK.
On board crystal is = 24.576MHz

In the datasheet, it tells to turn on the Dual rate for the same fs(ref). And NDAC and NADC = 0.5 (where do i set that value or is it default?)
Anyway, I set the relevant DAC and ADC dual rate bits in Page 0, Register 7 ...but it does not work.

For Fs = 48Khz
MCLK= 24.576MHz crystal , BCLK (from DSP) = 3.072 MHz, WCLK (from DSP) = 48kHz. (2 TDM slots for Stereo Audio and 32 bit /word)

For Fs = 96Khz
MCLK= 24.576MHz crystal , BCLK (from DSP) = 6.144 MHz, WCLK (from DSP) = 96kHz. (2 TDM slots for Stereo Audio and 32 bit /word)

So the Codec receives 96kHz signal even though its Fs(ref) is set at 48kHz. Where is it causing a problem?

over 8 years ago

0 Sherry Ismail over 8 years ago

Intellectual 885 points

I use oscilloscope to verify the BCLK and WCLK coming out of DSP and they are same as stated above. The code that checks users selected fs is below

switch (fs) {
	case 48000:
		AIC3106_writeRegister(7, (0 << 7) |// fs(ref) = 48kHz (needed only for AGC time constants, not used)
				(0 << 6) |	// ADC dual rate mode is disabled
				(0 << 5) |	// DAC dual rate mode is disabled
				(1 << 3) |	// left DAC datapath plays left channel input data
				(1 << 1) |	// right DAC datapath plays right channel input data
				(0 << 0));	// reserved
		//0x0A);
		break;
	case 96000:
		AIC3106_writeRegister(7, (0 << 7) |// fs(ref) = 48kHz (needed only for AGC time constants, not used)
				(1 << 6) |	// ADC dual rate mode is enabled
				(1 << 5) |	// DAC dual rate mode is enabled
				(0 << 4) |
				(1 << 3) |	// left DAC datapath plays left channel input data
				(0 << 2) |
				(1 << 1) |	// right DAC datapath plays right channel input data
				(0 << 0));	// reserved
		//0x0A);
		break;
	}

Any help please?

0 Luis Fernando Rodriguez S. over 8 years ago

TI__Guru* 84915 points

Hi, Sherry,

In dual-rate mode, the fs(ref) must fall within 39kHz to 53kHz. So, fs(ref) should be 48kHz in this case. Then, when the dual-rate mode is enabled (page 0, register 7), the fs(ref) is actually divided by 0.5 and then, the NADC/NDAC divider is applied. In your case, you would need to configure Q = 4 (page 0, register 3) and NADC/NDAC as 1 (page 0, register 2). This will result in fs=24.576MHz/(128*Q*NDAC*0.5)=96kHz.

I hope this helps you. Please let me know if the problem persists.

Best regards,
Luis Fernando Rodríguez S.

0 Sherry Ismail over 8 years ago in reply to Luis Fernando Rodriguez S.

Intellectual 885 points

Thanks, I have the same settings as you described. Silence from codec. This is what I have

register 3 = 0x22; //Q=4, P=2
register 2 = 0; //ADC and DAC fs = fs(ref)/1
switch (fs)
{
case 48000:
register 7 = 0x0A; //dual mode disabled and fs(ref) = 48kHz
break;
case 96000:
register 7 = 0x6A; //dual mode enabled and fs(ref)= 48kHz.
break;
}
register 8....
register 9....

PLL disabled and not used. Basically everything is the same as for 48kHz ( and that works fine)...

0 Sherry Ismail over 8 years ago in reply to Luis Fernando Rodriguez S.

Intellectual 885 points

As you said, the fs(ref) must be in the range 39kHz to 53kHz but my processor provides 96kHz for 96kHz option (Not 48kHz). Is that OK for codec?
The codec is set up to chose MCLK as CLKDIV_IN (register 102) and uses it to calculate CODEC_CLK (register 101)... so it should be good,, right?

processor outputs are connected to oscilloscope, and processor has communicated on 96kHz with external codec before. So I don't know what is going on :-(

0 Luis Fernando Rodriguez S. over 8 years ago in reply to Sherry Ismail

TI__Guru* 84915 points

Hi, Sherry,

It is fine if the processor provides 96kHz to the WCLK. The fs(ref) is actually the frequency value before the dividers. I mean that fs(ref) must be 48kHz and then this frequency will be divided by (0.5*NDAC). If NDAC is 1, the fs value will be 48kHz/0.5 = 96kHz.

I used the next register configuration on the TLV320AIC3106EVM. It worked with the same clock values that you are using.

w 30 07 6A
w 30 6D C0
w 30 03 20
w 30 2B 00
w 30 2C 00
w 30 25 C0
w 30 52 80
w 30 5C 80
w 30 56 09
w 30 5D 09

This register sequence configures the line outputs to be used with the DAC outputs. The code format is w(write) 30 (I2C address) 07 (register) 6A (data).

Could you try with this sequence to determine if the problem is related with a registers configuration or with the circuit?

Thank you.

Best regards,
Luis Fernando Rodríguez S.

Audio

Audio forum

AIC3106 sampling rate 96 kHz