Hello
I need some with allowing the EVM to take mic audio in and loop thru the DSP to audio out
Thank you
TOM
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Hello
I need some with allowing the EVM to take mic audio in and loop thru the DSP to audio out
Thank you
TOM
Hi, Tom,
Please take a look of the following script. It is an example configuration of how to use the on-board microphone.
############################################### # On-Board Differential Microphone # --------------------------------------------- # PowerTune mode PTM_R4 is used for high # performance 16-bit audio. # # For normal USB Audio, no hardware change # is required. # # If using an external interface, SW2.4 and # SW2.5 of the USB-ModEVM must be set to # HI and clocks can be connected to J14 of # the USB-ModEVM. # # IN3L/R is are routed differentially to the # LADC. ############################################### ############################################### # Software Reset ############################################### # # Select Page 0 w 30 00 00 # # Initialize the device through software reset w 30 01 01 # ############################################### ############################################### # Clock Settings # --------------------------------------------- # The codec receives: MCLK = 11.2896 MHz, # BLCK = 2.8224 MHz, WCLK = 44.1 kHz ############################################### # # Select Page 0 w 30 00 00 # # NADC = 1, MADC = 2 w 30 12 81 82 # ############################################### ############################################### # Signal Processing Settings ############################################### # # Select Page 0 w 30 00 00 # # Set the ADC Mode to PRB_P1 w 30 3d 01 # ############################################### ############################################### # Initialize Codec ############################################### # # Select Page 1 w 30 00 01 # # Disable weak AVDD in presence of external # AVDD supply w 30 01 08 # # Enable Master Analog Power Control w 30 02 00 # # Select ADC PTM_R4 w 30 3d 00 # # Set the input powerup time to 3.1ms (for ADC) w 30 47 32 # # Set the REF charging time to 40ms w 30 7b 01 # ############################################### ############################################### # Recording Setup ############################################### # # Select Page 1 w 30 00 01 # # Powerup MIC BIAS w 30 33 40 # # Route IN3L to LEFT_P with 10K input impedance w 30 34 04 # # Route IN3R to LEFT_M with 10K input impedance w 30 36 04 # # Unmute Left MICPGA w 30 3b 00 # # Unmute Right MICPGA w 30 3c 00 # # Select Page 0 w 30 00 00 # # Power up LADC/RADC w 30 51 c0 # # Unmute LADC/RADC w 30 52 00 # ###############################################
In order to use the on-board microphone, it would be necessary to install the jumpers as described on the 2.2.2 TLV320AIC3254 Jumper Locations section.
I hope this helps you. Please let me know if you have more questions or comments.
Best regards,
Luis Fernando Rodríguez S.
Hi, Tom,
I apologize for this confusion.
Please take a look of the following script:
############################################### # High Performance Stereo Recording # --------------------------------------------- # PowerTune mode PTM_R4 is used for high # performance 16-bit audio. # # IN2L/R is routed to the LADC/RADC in a # single-ended manner. ############################################### ############################################### # Software Reset ############################################### # # Select Page 0 w 30 00 00 # # Initialize the device through software reset w 30 01 01 # ############################################### ############################################### # Clock Settings # --------------------------------------------- # The codec receives: MCLK = 11.2896 MHz, # BLCK = 2.8224 MHz, WCLK = 44.1 kHz ############################################### # # Select Page 0 w 30 00 00 # # NADC = 1, MADC = 2 w 30 12 81 82 # ############################################### ############################################### # Signal Processing Settings ############################################### # # Select Page 0 w 30 00 00 # # Set the ADC Mode to PRB_P1 w 30 3d 01 # ############################################### ############################################### # Configure Power Supplies ############################################### # # Select Page 1 w 30 00 01 # # Power up AVDD LDO w 30 02 A9 # # Disable weak AVDD in presence of external # AVDD supply w 30 01 08 # # Enable Master Analog Power Control # Power up AVDD LDO w 30 02 A1 # # Set the input power-up time to 3.1ms (for ADC) w 30 47 32 # # Set the REF charging time to 40ms w 30 7b 01 # ############################################### ############################################### # Recording Setup ############################################### # # Select Page 1 w 30 00 01 # # Route IN3L to LEFT_P with 20K input impedance w 30 34 08 # # Route CM1L to LEFT_M with 20K input impedance w 30 36 80 # # Route IN3R to RIGHT_P with 20K input impedance w 30 37 08 # # Route CM1R to RIGHT_M with 20K input impedance w 30 39 80 # # Enable MICBIAS w 30 33 40 # # Unmute Left MICPGA, Gain selection of 6dB to make channel gain 0dB # Register of 6dB with input impedance of 20K => Channel Gain of 0dB w 30 3b 0c # # Unmute Right MICPGA, Gain selection of 6dB to make channel gain 0dB # Register of 6dB with input impedance of 20K => Channel Gain of 0dB w 30 3c 0c # # Select Page 0 w 30 00 00 # # Power up LADC/RADC w 30 51 c0 # # Unmute LADC/RADC w 30 52 00 # ###############################################
Best regards,
Luis Fernando Rodríguez S.
Hi, Tom,
The original script was taken from a single-ended configuration. It is already modified to use a differential input even if the comments refers to the original script (IN2L/R in single-ended configuration). Additionally, the MICBIAS is provided by the script.
Finally, regarding your last question, the TLV320AIC3254EVM-U GUI has a command-line interface window where this script can be loaded.
I hope this helps you. Please let me know if you have more questions or comments.
Best regards,
Luis Fernando Rodríguez S.
Hi, Tom,
The EEPROM Manager is a specific tool of the TLV320AIC3254-U. The bottom of the page specifies that it is not compatible with the TLV320AIC3254-U Ver. A. Please take a look at the attached document. It gives a little explanation about the EEPROM Manager.
7776.How to Flash EEPROM to AIC3254 EVM.pdf
Regarding your application on PPS, I suggest to create an algorithm as the following. It contains all the elements that you requested. However, the AEC block is not supported by our codecs:
Finally, in order to configure the registers by PPS, I suggest to use the following script:
;----------------------------------------------------------------------------------- ; Software Reset ;----------------------------------------------------------------------------------- reg[ 0][ 1] = 0x01 ; Initialize the device through software reset reg[254][ 0] = 0x0a ; Delay 10ms ;----------------------------------------------------------------------------------- ; Configure Power Supplies ;----------------------------------------------------------------------------------- %%if (%%prop(TargetBoard) == 2) ; AIC3254EVM-U specific configuration reg[ 1][ 2] = 0xa9 ; Power up AVDD LDO reg[ 1][ 1] = 0x08 ; Disable weak AVDD to DVDD connection reg[ 1][ 2] = 0xa1 ; Enable Master Analog Power Control, AVDD LDO Powered %%else ; AIC3254EVM-K specific configuration reg[ 1][ 1] = 0x08 ; Disable weak AVDD to DVDD connection reg[ 1][ 2] = 0x00 ; Enable Master Analog Power Control %%endif reg[ 1][ 71] = 0x32 ; Set the input power-up time to 3.1ms reg[ 1][123] = 0x01 ; Set REF charging time to 40ms (automatic) ; reg[254][0] = 0x28 ; Delay 40ms for REF to Power Up ;----------------------------------------------------------------------------------- ; Load miniDSP Code ;----------------------------------------------------------------------------------- PROGRAM_ADC ; miniDSP_A coefficients and instructions PROGRAM_DAC ; miniDSP_D coefficients and instructions ;----------------------------------------------------------------------------------- ; Signal Processing Settings ;----------------------------------------------------------------------------------- %%if (%%prop(SynchMode) == 1) ; SynchMode is enabled reg[ 0][ 60] = 0x80 ; DAC prog Mode: miniDSP_A and miniDSP_D ARE powered up together, miniDSP_A used for signal processing %%else ; SynchMode is disabled reg[ 0][ 60] = 0x00 ; DAC prog Mode: miniDSP_A and miniDSP_D NOT powered up together, miniDSP_A used for signal processing %%endif reg[ 0][ 61] = 0x00 ; Use miniDSP_A for signal processing %%if ("%%prop(FrameworkType)" == "AIC3254App8x4x") reg[ 0][ 17] = 0x08 ; 8x Interpolation reg[ 0][ 23] = 0x04 ; 4x Decimation %%endif %%if ("%%prop(FrameworkType)" == "AIC3254App4x2x") reg[ 0][ 17] = 0x04 ; 4x Interpolation reg[ 0][ 23] = 0x02 ; 2x Decimation %%endif %%if ("%%prop(FrameworkType)" == "AIC3254App2x1x") reg[ 0][ 17] = 0x02 ; 2x Interpolation reg[ 0][ 23] = 0x01 ; 1x Decimation %%endif IDAC = %%prop(miniDSP_D_Cycles) IADC = %%prop(miniDSP_A_Cycles) %%if (%%prop(miniDSP_A_Adaptive) == 1) reg[ 8][ 1] = 0x04 ; adaptive mode for ADC %%endif %%if (%%prop(miniDSP_D_Adaptive) == 1) reg[ 44][ 1] = 0x04 ; adaptive mode for DAC %%endif ;----------------------------------------------------------------------------------- ; Clock and Interface Configuration ;----------------------------------------------------------------------------------- ; USB Audio supports 8kHz to 48kHz sample rates ; An external audio interface is required for 88.2kHz to 192kHz sample rates ;----------------------------------------------------------------------------------- %%if (%%prop(SampleRate) == 176400 || %%prop(SampleRate) == 192000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 32 (MSB) reg[ 0][ 14] = 0x20 ; DOSR = 32 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on reg[ 0][ 20] = 0x20 ; AOSR = 32 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 88200 || %%prop(SampleRate) == 96000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 64 (MSB) reg[ 0][ 14] = 0x40 ; DOSR = 64 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on reg[ 0][ 20] = 0x40 ; AOSR = 64 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 128 (MSB) reg[ 0][ 14] = 0x80 ; DOSR = 128 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 32000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x00 ; DOSR = 192 (MSB) reg[ 0][ 14] = 0xc0 ; DOSR = 192 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x8c ; MADC = 12, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 22050 || %%prop(SampleRate) == 24000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8 reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x01 ; DOSR = 256 (MSB) reg[ 0][ 14] = 0x00 ; DOSR = 256 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x90 ; MADC = 16, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 16000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24 reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x01 ; DOSR = 384 (MSB) reg[ 0][ 14] = 0x80 ; DOSR = 384 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0x98 ; MADC = 24, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 11025) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=16 reg[ 0][ 6] = 0x10 ; P=1, R=1, J=16 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x02 ; DOSR = 512 (MSB) reg[ 0][ 14] = 0x00 ; DOSR = 512 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0xa0 ; MADC = 32, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif %%if (%%prop(SampleRate) == 8000) reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24 reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24 reg[ 0][ 7] = 0x00 ; D=0000 (MSB) reg[ 0][ 8] = 0x00 ; D=0000 (LSB) reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on reg[ 0][ 13] = 0x03 ; DOSR = 768 (MSB) reg[ 0][ 14] = 0x00 ; DOSR = 768 (LSB) reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off reg[ 0][ 19] = 0xb0 ; MADC = 48, divider powered on reg[ 0][ 20] = 0x80 ; AOSR = 128 reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on %%endif ;----------------------------------------------------------------------------------- ; ADC Channel Configuration ;----------------------------------------------------------------------------------- reg[ 1][ 51] = 0x40 ; Mic Bias enabled, Source = Avdd, 1.25V %%if (%%prop(TargetBoard) == 2) ; AIC3254EVM-U specific configuration reg[ 1][ 52] = 0x04 ; Route IN3L to LEFT_P with 10K input impedance reg[ 1][ 54] = 0x04 ; Route IN3R to LEFT_M with 10K input impedance %%else ; AIC3254EVM-K specific configuration reg[ 1][ 52] = 0x40 ; Route IN1L to LEFT_P with 10K input impedance reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance reg[ 1][ 55] = 0x40 ; Route IN1R to RIGHT_P with 10K input impedance %%endif reg[ 1][ 57] = 0x40 ; Route CM1R to RIGHT_M with 10K input impedance reg[ 1][ 59] = 0x00 ; Enable MicPGA_L Gain Control, 0dB reg[ 1][ 60] = 0x00 ; Enable MicPGA_R Gain Control, 0dB reg[ 0][ 81] = 0xc0 ; Power up LADC/RADC reg[ 0][ 82] = 0x00 ; Unmute LADC/RADC ;----------------------------------------------------------------------------------- ; DAC Channel Configuration ;----------------------------------------------------------------------------------- reg[ 1][ 20] = 0x25 ; De-pop: 5 time constants, 6k resistance reg[ 1][ 12] = 0x08 ; Route LDAC to HPL reg[ 1][ 13] = 0x08 ; Route RDAC to HPR reg[ 1][ 14] = 0x08 ; Route LDAC to LOL reg[ 1][ 15] = 0x08 ; Route LDAC to LOR reg[ 0][ 63] = 0xd4 ; Power up LDAC/RDAC w/ soft stepping reg[ 1][ 16] = 0x00 ; Unmute HPL driver, 0dB Gain reg[ 1][ 17] = 0x00 ; Unmute HPR driver, 0dB Gain reg[ 1][ 18] = 0x00 ; Unmute LOL driver, 0dB Gain reg[ 1][ 19] = 0x00 ; Unmute LOR driver, 0dB Gain reg[ 1][ 9] = 0x3c ; Power up HPL/HPR and LOL/LOR drivers reg[ 0][ 64] = 0x00 ; Unmute LDAC/RDAC
It must be placed on the SystemSettingsCode Property of the AIC3254 framework.
Best regards,
Luis Fernando Rodríguez S.