Dear Sirs
I use AIC3204 for my new project.
The schematic is shown as follow.
But AIC3204 could not work. Could you help me review the circuit? Thanks
BRS
Nat
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Dear Sirs
I use AIC3204 for my new project.
The schematic is shown as follow.
But AIC3204 could not work. Could you help me review the circuit? Thanks
BRS
Nat
Dear Luis
The following txt is my register setting.
I want to use HP function.
But my HP function does not work.
Could you help me to check? Thanks
===============================================
# MICBIAS powered up; AVDD selected
w 30 33 70
#
# Route IN1L to LEFT_P with 20K input impedance
w 30 34 80
#
# Route Common Mode to LEFT_M with impedance of 20K
w 30 36 80
#
# Route IN1R to RIGHT_P with input impedance of 20K
w 30 37 80
#
# Route Common Mode to RIGHT_M with impedance of 20K
w 30 39 80
#
# Unmute Left MICPGA, Gain selection of 6dB to make channel gain 0dB
# Register of 6dB with input impedance of 20K => Channel Gain of 0dB
w 30 3b 0c
#
# Unmute Right MICPGA, Gain selection of 6dB to make channel gain 0dB
# Register of 6dB with input impedance of 20K => Channel Gain of 0dB
w 30 3c 0c
#
# Select Page 0
w 30 00 00
#
# Power up LADC/RADC
w 30 51 c0
#
# Unmute LADC/RADC
w 30 52 00
#
###############################################
###############################################
# Playback Setup
###############################################
#
# Select Page 1
w 30 00 01
#
# De-pop
w 30 14 25
#
# Route MAL/MAR to HPL/HPR
w 30 0c 02 02
#
# Power up HPL/HPR and MAL/MAR
w 30 09 33
#
# Unmute HPL/HPR driver, 0dB Gain
w 30 10 00 00
#
###############################################
===============================================
BRS
Nat
Hi, Nat,
Could you add the following lines to your code?
# Page 0 selected
w 30 00 00
#
# Software reset
w 30 01 01
#
# Clock settings
w 30 04 03 91 08
w 30 0D 00 80
w 30 14 80
w 30 0B 82 88
w 30 12 82 88
#
# Disable weak AVDD-DVDD connection
w 30 00 01
w 30 01 08
#
# Power up analog blocks
w 30 02 00
Please let me know if the problem persists.
Best regards,
Luis Fernando Rodríguez S.