TLV320AIC3107EVM BLCK setting

Hi, Huy,

The TLV320AIC3107EVM provides a default BCLK and WCLK from the TAS1020b. These clocks can be disabled by the SW2 of the MODEVM-INTERFACE board. If you're looking to implement a different clock, there are two ways to do it:

1) Disable the I2S lines (BCLK/WCLK) by the SW2. Then, connect external BCLK and WCLK with the desired values.
2) Disable the I2S lines. Configure the TLV320AIC3107EVM in master mode (BCLK and WCLK as outputs).

Please let me know if you have questions or comments.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

I see on SW2 has level LO and HI when I change switch to HI it mean disable the switch select.

Now I set SW 2 is  (EXT MCK, USB RST, USB SPI, USB MCLK, USB I2S) HI level and (A0,A1,A2) LO level. Is it right to disable clocks ?

On my app, I use Dk-TM4C129x to transfer audio data to TLV320AIC3107EVM.

- I use DK-TM4c129x which sysclock 120Mhz , generate MCLK   12Mhz. for TLV320AIC3107EVM.

- Configure TLV320AIC3107 register control PLL follow data sheet.

- I check WCLK signal is 8Khz and BCLK is 1.4Mhz.

When I playback audio file 8000Hz_16bit_PCM, I see data transfer so fast. The speed is 80000bytes/s. So I only hear the noise signal at HP-OUTPUT.

Please give me some advice about transfering audio data. How to improve it ? I base on www.ti.com/.../spma042b.pdf

Thanks,

Huy Huynh

Hi, Huy,

In order to use external MCLK and external WCLK/BCLK, it is necessary to disable the USB MCLK and USB I2S. So, both switches must be in HI state as you mentioned. EXT MCK must be placed in HI state as well. The rest of the switches must be placed in LO state.

Then, you must be sure that BCLK is calculated as BCLK = WCLK * (# bits) * (# channels).

I suggest to take a look at this document: www.ti.com/.../slaa403.pdf. It is about the TLV320AIC3104 but it applies for the TLV320AIC3107 too.

If the problem persists, could you provide your register configuration, please?

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

The BCLK value which I measure on TLV320AIC3107EVM, doesn't follow formular you provide.

The value of WCLK is 8khz but the value of BCLK is 1.4Mhz.

This is my register configuration:

//
    // Codec Data Path Register
    // ----------------------
    // Fsref = 44.1kHz.
    // Left DAC datapath plays left channel input data.
    // Right DAC datapath plays right channel input data.
    // ----------------------
    // D[7:0] = 1000 1010
    //
    DACWriteRegister(7, 0x8A);

    //
    // Audio Serial Data Interface Control Register A
    // ----------------------
    // BCLK is an output (master mode)
    // WCLK is an output (master mode)
    // BCLK/WCLK will continue to be transmitted when running in master mode.
    // ----------------------
    // D[7:0] = 1101 0000
    //
    DACWriteRegister(8, 0xD0);
    //
    // Audio Serial Data Interface Control Register B
    // ----------------------
    // Serial data bus uses I2S mode.
    // Audio data word length = 16-bits.
    // ----------------------
    // D[7:0] = 0000 0000
    //        
    DACWriteRegister(9, 0x00);
    //
    // PLL Programming Register B
    // ----------------------
    // J = 7
    // ----------------------
    // D[7:0] = 0001 1100
    //    
    DACWriteRegister(4, 0x1C);
    //
    // PLL Programming Register B
    // ----------------------
    // J = 7
    // ----------------------
    // D[7:0] = 0001 1100
    //    
    DACWriteRegister(4, 0x1C);
    
    //
    // PLL Programming Register C
    // ----------------------
    // D most significant bits
    // ----------------------
    // D[7:0] = 0101 0010
    //    
    DACWriteRegister(5, 0x52);
    
    //
    // PLL Programming Register D
    // ----------------------
    // D least significant bits
    // ----------------------
    // D[7:0] = 0100 0000
    //    
    DACWriteRegister(6, 0x40);
    
    //
    // PLL Programming Register A
    // ----------------------
    // PLL is enabled.
    // Q = 2.
    // P = 1.
    // ----------------------
    // D[7:0] = 1001 0010 
    //   
    DACWriteRegister(3, 0x91);
    //
    // Headset/Button Press Detection Register A
    // ----------------------
    // Headset detection enabled.
    // ----------------------
    // D[7:0] = 1000 0000
    //   
    DACWriteRegister(13, 0x80);

    //
    // Headset/Button Press Detection Register B
    // ----------------------
    // Configure to stereo fully-differential output
    // ----------------------
    // D[7:0] = 0100 0000
    //   
    DACWriteRegister(14, 0x40);

    //
    // DAC Output Switching Control Register
    // ----------------------
    // Left DAC output selects DAC_L1 path
    // Right DAC output selects DAC_R1 path
    // Left and right DAC channels have independent volume controls.
    // ----------------------
    // D[7:0] = 0000 0000
    //   
    DACWriteRegister(41, 0x00);

    //
    // Left DAC Digital Volume Control Register
    // ----------------------
    // The left DAC is not muted.
    // Gain = 0.0dB.
    // ----------------------
    // D[7:0] = 0000 0000
    //   
    DACWriteRegister(43, 0x00);

    //
    // Right DAC Digital Volume Control Register
    // ----------------------
    // The right DAC channel is not muted.
    // Gain = 0.0dB.
    // ----------------------
    // D[7:0] = 0000 0000 
    //   
    DACWriteRegister(44, 0x00);

    //
    // Codec Sample Rate Select Register
    // ----------------------
    // DAC Fs = Fsref/5.5
    // ----------------------
    // D[7:0] = 0000 1001
    //   
    DACWriteRegister(2, 0x09);

    //
    // DAC_L1 to HPLOUT Volume Control Register
    // ----------------------
    // DAC_L1 is routed to HPLOUT.
    // ----------------------
    // D[7:0] = 1000 0000
    //   
    DACWriteRegister(47, 0x80);

    //
    // DAC_R1 to HPROUT Volume Control Register
    // ----------------------
    // DAC_R1 is routed to HPROUT.
    // ----------------------
    // D[7:0] = 1000 0000
    //   
    DACWriteRegister(64, 0x80);

    //
    // DAC Power and Output Driver Control Register
    // ----------------------
    // Left DAC is powered up.
    // Right DAC is powered up.
    // ----------------------
    // D[7:0] = 1100 0000
    //     
    DACWriteRegister(37, 0xC0);
    DACWriteRegister(102, 0x02);
    //
    // Using L2/R2 bypasses the analog volume controls & mixing  networks. This
    // output provides the highest quality DAC playback performance with 
    // reduced power dissipation. Note: This can only be utilized if the DAC
    // output does not need to route to multiple output drivers simultaneously,
    // and if mixing of the DAC output with other analog signals is not needed. 
    // If mixing isdesired, L1/R2 would be utilized. However, for our
    // differential headpones/speakers, this will suffice.
    //
    // DAC Output Switching Control Register
    // ----------------------
    // Left DAC output selects DAC_L2 path to left high power output drivers.
    // Right DAC output selects DAC_R2 path to right high power output drivers.
    // ----------------------
    // D[7:0] = 1010 0000
    //   
    DACWriteRegister(41, 0xA0);

    //
    // Output Driver Pop Reduction Register
    // ----------------------
    // Driver power-on time = 400mS.
    // Driver ramp-up step time = 0mS.
    // ----------------------
    // D[7:0] = 1000 0000
    //   
    DACWriteRegister(42, 0x80);

    //
    // HPROUT Output Level Control Register
    // ----------------------
    // Output level control = 0dB.
    // HPROUT is not muted.
    // HPROUT is weakly driven to a common-mode when powered down.
    // HPROUT is fully powered up.
    // ----------------------
    // D[7:0] = 0000 1101
    //         
    DACWriteRegister(65, 0x0D);

    //
    // HPLOUT Output Level Control Reigster
    // ----------------------
    // Output level control = 0dB.
    // HPLOUT is not muted.
    // HPLOUT is weakly driven to a common-mode when powered down.
    // HPLOUT is fully powered up. 
    // ----------------------
    // D[7:0] = 0000 1101
    //    
    DACWriteRegister(51, 0x0D);

    //
    // Left DAC Digital Volume Control Register
    // ----------------------
    // Gain = -30dB.
    // ----------------------
    // D[7:0] = 0010 1100
    //    
    DACWriteRegister(43, pucVolumeTable[50 / 10 - 1]);

    //
    // Right DAC Digital Volume Control Register
    // ----------------------
    // Gain = -30dB.
    // ----------------------
    // D[7:0] = 0011 1100
    //   
    DACWriteRegister(44, pucVolumeTable[3]);

    //
    // Codec Datapath Setup Register
    // ----------------------
    // Fsref = 44.1kHz.
    // DAC dual rate mode is disabled.
    // LEFT DAC datapath plays left channel input data.
    // RIGHT DAC datapath plays right channel input data.
    // ----------------------
    // D[7:0] = 1000 1010
    //   
    //DACWriteRegister(7, 0xAA);
      DACWriteRegister(7, 0x8A);
    //
    // Codec Sample Rate Select Register
    // ----------------------
    // DAC Fs = Fsref/2
    // ----------------------
    // D[7:0] = 0000 1001
    //   
    DACWriteRegister(2, 0x09);

Please help me check it.

Thanks,

Huy Huynh