TLV320AIC3100 Linux Register Settings

Hi, Brian,

Could you provide the actual register configuration to have a better approach to this issue? Also, could you provide the WCLK and BCLK frequencies?

Best regards,
Luis Fernando Rodríguez S.

Here are the register settings we think we need.

We could be missing some other path enable but I think it may be the
clock dividers where we are going wrong. e.g. Reg 11 and 12 and may be others as well

The source is 44.1kHz, the word is 16 bit, i.e. the bclk is 44.1 x 16 x 2 == 1.4112 MHz
Wclk is bclk/32 (i.e. 16 bclks per word).


Regiter addresses are decimal (not hex)

Page 0, Reg 4 set 0x05 == select the bclk
Page 0, Reg 11 set 0x81 == DAC clock divider and setting
Page 0, Reg 12 set 0x81 == DAC clock divider and setting
Page 0, Reg 63 set 0xd4 == DAC Path Setup
Page 0, Reg 64 set 0x00 == DAC mute control
Page 0, Reg 65 leave default == DAC Volume Control

Change page by writing to Reg 0

Page 1, Reg 32 set 0x86 == Class D Amplifier Control
Page 1, Reg 35 set 0x44 == DAC Mixer Routing
Page 1, Reg 38 set 0x80 == Analog vol control - enable 0dB
Page 1, Reg 42 set 0x05 == Speaker Driver Mute & Final gain stage

So an update.

We have audio on the output but I am pretty sure that the sampling/DAC/oversampling is not set correctly.

So for the case outlined above can we get settings for the DAC clock setup.

The IC specification doesn't really give enough information to understand optimal settings for NDAC, MDAC, DOSR etc.

Hi, Geoff,

Thank you for provide the register configuration.

I have been checking the entire register settings and it seems that the sampling rate is not being configured correctly. It would be necessary the usage of the PLL in order to get the correct sample rate. This configuration gives a sample rate of fs = BCLK / DOSR = 1.4112MHz / 128 = 11.025 kHz.

So, in order to get 44.1kHz, it would be necessary to configure page 0 / registers 5 - 14 correctly. I suggest to use the next PLL and dividers values:

R = 2; J = 32; P = 1; D = 0
NDAC = MDAC = 4
DOSR = 128

These values will configure the sample rate as:

fs = BCLK * (R * J.D ) / (P * NDAC * MDAC * DOSR) = 44.1KHz

Please let me know if you have questions or comments about this.

Best regards,
Luis Fernando Rodríguez S.

This seems to have vastly improved the sound quality.

Thanks

Geoff

Settings for audio out (as above) seem to be good.

We need similar guidance on setting for audio in  (44.1, 16 bit).

We have a knowles single-ended microphone on MIC1RP

It puts out about 10mv

We would like some guidance on the clock and gain settings.

In particular we are confused about what you might want done with the CM negative input.

Does the PGA self-bias, or are we required to bias via the CM.  

The chip spec is a little light on for detail here.

Hi, Geoff,

This should be the same register configuration for audio in. The clock settings can be set for the ADC as:

R = 2; J = 32; P = 1; D = 0
NADC = MADC = 4
AOSR = 128

Additionally, in case of CM voltage, I suggest to route it internally to the M-terminal with RIN = 10kohm.

Please let me know if you have more questions or comments.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

 

TI previously optimized the TLV320AIC3100 settings to 44.1 CD level setting.

 

However, customer now needs an optimized setting for 16kHz sampling of the Audio In (and Audio Out, but Audio In is the most important).  This is required for audio analytics and also to support Amazon Voice Services - both of these require 16kHz sampling.

 

The current 44.1 CD settings have issues with aliasing and DC offset.  Therefore, they require optimized register suggestions to allow 16K sampling with appropriate anti-alias measures in the codec filters.

 

The DC component is something they have noticed but have not been concerned with until now.

They AC couple the microphone and set a common mode on the front end codec amplifier.  So they think the offset is coming from inside the codec's front end.  Perhaps they have the configuration not quite right or maybe a DC offset is a known issue?

 

Please advise as this is a high priority now because they built 200 proto units and need to resolve this before going to production.

 

Thanks!

Brian

Hi, Brian,

In case of a 16KHz sampling, there are several considerations to take. Since WCLK = fs = 16KHz, BCLK must be changed to be at least BCLK = 64*WCLK = 1.024MHz. Also, this would change the PLL coefficient values:

R = 6; J = 14; P = 1; D = 0
NADC = MDAC = 7; MADC = NDAC = 6
AOSR = 128

Regarding the DC offset, could you tell me which value it has?

Thank you.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

Thanks for the above.

I have some questions:

1. did you really mean NADC=MDAC=7, I just assumed it would be NADC=NDAC  and MADC=MDAC  etc.

2. why is BCLK = 64*WCLK  = 1.024 when for the 44.1khz case its BCLK = 1.4112  (aka 32*).  i.e. we're doing 16 bit stereo words at 16000 = 512000 bit clock

3. is there another doc that goes into more detail on the rational for the NADC, MADC selections etc,, i.e. the oversampling adc constraints etc, anti-aliasing considertions etc.  The 3100 spec is a bit light on in this area

I guess my main question is we're providing an analog  signal off the microphone with components above 8kHz, do the above settings adequately deal with enough oversampling and anti-aliasing so that we can have 16k sampling?

Hi, Geoff,

1. Yes, it is possible both cases NADC = MDAC or NADC = NDAC.

2. We recommend this value since DOSR range normally is limited by 2.8MHz < DOSR * DAC_FS < 6.2MHz. Also, these settings follow the PLL conditions of datasheet. If these conditions are respected, then there won't be any aliasing issue.

3. All the documentation about the TLV320AIC3100 is located in the product folder (www.ti.com/.../technicaldocuments). However, there's no additional information about the PLL and dividers values.

Regarding the DC offset, our codec devices have biquad filters that can be configured as high-pass filters. These would eliminate the DC components.

Finally, in this case it would be necessary to use a higher sampling rate. The components above 8KHz are not in the conditions of the decimation filters. Please take a look at the Decimation filters section of datasheet to see the respective frequency responses: www.ti.com/.../slas667b.pdf

Best regards,
Luis Fernando Rodríguez S.