AIC3120 noise

Hi, David,

There are few functions on the TLV320AIC3120 GUI that cannot be changed by the blocks. It would be necessary to use the register inspector tool on the view menu in order to disable the headphone and Class-D amplifier.

Could you provide the sampling rate of the EVM? Also, could you provide the clock frequencies that the EVM is using?

Thank you.

Best regards,
Luis Fernando Rodríguez S.

I understand.  

So I'm just using the Codec Control program for the EVM now. All I do is plug the EVM in, load the CC software and let it connect, then enable the ADC-DAC loopback, feed audio into the "mic in" socket and then connect the "HP output" to my +26db amplifier

The noise is terrible. 

I have tried

1) Disabling the class-d amplifier

2) Putting the HP amplifier into lineout mode.

Neither have any effect. Can this codec be used in this way? I.e Line in - ADC - miniDSP processing - DAC - line out

I don't understand why it is so noisy. Perhaps the ADC is set up for microphone input and the gain is too high? I'm not sure. 

What do you suggest? 

- David

I've gone even simpler than this. 

I've just plugged the EVM into my PC, selected "USB-AudioEVM" as my playback device to stream I2S audio from the PC to the board. Then opened up the CodecControl program. 

It starts up and plays music straight away but there is lots of background noise/hiss. 

What is wrong? The Codec can't possibly be this noisy. 

- David

Hi, David,

The default settings of the EVM don't work correctly with all the sampling rates. So, could you provide your clock settings (BCLK, WCLK, MCLK) in order to provide the correct PLL values, please?

Thank you.

Best regards,
Luis Fernando Rodríguez S.

I haven't touched any of the system settings code. Remember, I am using the AIC3120EVM board... I think this has an onboard 11.2896MHz osc.

This is what it has created, can you recommend what I should change?

reg[0][1] = 0x01 ; S/W Reset
reg[0][4] = 0x03 ; PLL_CLKIN = MCLK = 11.2896 MHz., CODEC_CLKIN=PLL_CLK
reg[0][5] = 0x91 ; PLL Power Up, P = 1, R = 1
reg[0][6] = 0x08 ; J = 8
reg[0][7] = 0x00 ; D(13:8) = 0
reg[0][8] = 0x00 ; D(7:0) = 0 (CODEC_CLKIN = (PLL_CLKIN * R * J.D) / P = 90.3168 MHz.
reg[0][27] = 0x00 ; Mode = I2S, wordlength = 16

reg[43][95] = 0x00 ; (Bit 23-16) ------------ MSB ADC INST No. 383
reg[43][96] = 0x00 ; (Bit 15-8)
reg[43][97] = 0x00 ; (Bit 7-0)
reg[95][95] = 0x00 ; (Bit 23-16) ------------ MSB DAC INST No. 1023
reg[95][96] = 0x00 ; (Bit 15-8)
reg[95][97] = 0x00 ; (Bit 7-0)

IADC = %%prop(miniDSP_A_Cycles)
IDAC = %%prop(miniDSP_D_Cycles)
reg[0][60] = 0x40 ; DAC programmable mode, DAC miniDSP powered up even if DAC is powered down
reg[0][61] = 0x00 ; ADC programmable mode
PROGRAM_ADC
PROGRAM_DAC
%%if ("%%prop(FrameworkType)" == "AIC31XXApp2x1xAsynch" || "%%prop(FrameworkType)" == "AIC31XXApp2x1xSynch")
reg[0][13] = 0x00 ; DOSR = 32, DOSR(9:8) = 0
reg[0][14] = 0x20 ; DOSR = 32, DOSR(7:0) = 32 (DAC Fs = 5.6448 / 32 = 176.4 KHz.)
reg[0][16] = 0x02 ; Interpolation Ratio = 2
reg[0][20] = 0x20 ; AOSR = 32 (ADC Fs = 5.6448 / 32 = 176.4 KHz.)
reg[0][22] = 0x01 ; Decimation Ratio = 1
%%endif
%%if ("%%prop(FrameworkType)" == "AIC31XXApp4x2xAsynch" || "%%prop(FrameworkType)" == "AIC31XXApp4x2xSynch")
reg[0][13] = 0x00 ; DOSR = 64, DOSR(9:8) = 0
reg[0][14] = 0x40 ; DOSR = 64, DOSR(7:0) = 64 (DAC Fs = 5.6448 / 64 = 88.2 KHz.)
reg[0][16] = 0x04 ; Interpolation Ratio = 2
reg[0][20] = 0x40 ; AOSR = 64 (ADC Fs = 5.6448 / 64 = 88.2 KHz.)
reg[0][22] = 0x02 ; Decimation Ratio = 2
%%endif
%%if ("%%prop(FrameworkType)" == "AIC31XXApp8x4xAsynch" || "%%prop(FrameworkType)" == "AIC31XXApp8x4xSynch")
reg[0][13] = 0x00 ; DOSR = 128, DOSR(9:8) = 0
reg[0][14] = 0x80 ; DOSR = 128, DOSR(7:0) = 32 (DAC Fs = 5.6448 / 128 = 44.1 KHz.)
reg[0][16] = 0x08 ; Interpolation Ratio = 8
reg[0][20] = 0x80 ; AOSR = 128 (ADC Fs = 5.6448 / 128 = 44.1 KHz.)
reg[0][22] = 0x04 ; Decimation Ratio = 4
%%endif
reg[1][33] = 0x4e ; De-pop, Power on = 800 ms., Step time = 4 ms.
%%if (%%prop(Device) == 3111)
reg[1][31] = 0xc0 ; HPL and HPR powered up
%%else
reg[1][31] = 0x80 ; HPL powered up
%%endif
reg[1][35] = 0x88 ; LDAC routed to HPL, RDAC routed to HPR
reg[1][40] = 0x04 ; HPL unmute and gain 0db
%%if (%%prop(Device) == 3111)
reg[1][41] = 0x04 ; HPR unmute and gain 0db
%%endif
reg[1][48] = 0x40 ; MIC is selected for left Mic PGA P @ 10k input impedance
reg[1][49] = 0x40 ; CM is selected for left Mic PGA M @ 10k input impedance
reg[0][63] = 0xd6 ; Powerup DAC left and right channels (soft step disable)
reg[0][64] = 0x00 ; Unmute DAC left and right channels
reg[0][81] = 0x80 ; Powerup ADC channel
reg[0][82] = 0x00 ; Unmute ADC channel
%%if ("%%prop(FrameworkType)" == "AIC31XXApp2x1xAsynch" || "%%prop(FrameworkType)" == "AIC31XXApp4x2xAsynch" || "%%prop(FrameworkType)" == "AIC31XXApp8x4xAsynch")
reg[0][11] = 0x82 ; DAC Powerup NDAC = 2 (DAC_MAC_CLK = 90.3168 MHz/2 = 45.1584 MHz.)
reg[0][12] = 0x88 ; DAC Powerup MDAC = 8 (DAC_MOD_CLK = 45.1584/8 = 5.6448 MHz.)
reg[0][18] = 0x84 ; ADC Powerup NADC = 4 (ADC_MAC_CLK = 90.3168 MHz/4 = 22.5792 MHz.)
reg[0][19] = 0x84 ; DAC Powerup MADC = 4 (ADC_MOD_CLK = 22.5792/4 = 5.6448 MHz.)
%%endif
%%if ("%%prop(FrameworkType)" == "AIC31XXApp2x1xSynch" || "%%prop(FrameworkType)" == "AIC31XXApp4x2xSynch" || "%%prop(FrameworkType)" == "AIC31XXApp8x4xSynch")
reg[0][11] = 0x84 ; DAC Powerup NDAC = 4 (DAC_MAC_CLK = 90.3168 MHz/4 = 22.5792 MHz.)
reg[0][12] = 0x84 ; DAC Powerup MDAC = 4 (DAC_MOD_CLK = 22.5792/4 = 5.6448 MHz.)
reg[0][18] = 0x84 ; ADC Powerup NADC = 4 (ADC_MAC_CLK = 90.3168 MHz/4 = 22.5792 MHz.)
reg[0][19] = 0x84 ; DAC Powerup MADC = 4 (ADC_MOD_CLK = 22.5792/4 = 5.6448 MHz.)
%%endif
%%if (%%prop(miniDSP_D_Adaptive) == 1)
reg[8][1] = 0x04 ; Adaptive mode enabled for DAC
%%endif

;-----------------------------------------------------------------------------------
; Clock and Interface Configuration
;-----------------------------------------------------------------------------------
; USB Audio supports 8kHz to 48kHz sample rates
; An external audio interface is required for 88.2kHz to 192kHz sample rates
;-----------------------------------------------------------------------------------
%%if (%%prop(SampleRate) == 176400 || %%prop(SampleRate) == 192000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 32 (MSB)
reg[ 0][ 14] = 0x20 ; DOSR = 32 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on
reg[ 0][ 20] = 0x20 ; AOSR = 32
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on

%%endif

%%if (%%prop(SampleRate) == 88200 || %%prop(SampleRate) == 96000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 64 (MSB)
reg[ 0][ 14] = 0x40 ; DOSR = 64 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on
reg[ 0][ 20] = 0x40 ; AOSR = 64
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 128 (MSB)
reg[ 0][ 14] = 0x80 ; DOSR = 128 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 32000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x00 ; DOSR = 192 (MSB)
reg[ 0][ 14] = 0xc0 ; DOSR = 192 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x8c ; MADC = 12, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 22050 || %%prop(SampleRate) == 24000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x01 ; DOSR = 256 (MSB)
reg[ 0][ 14] = 0x00 ; DOSR = 256 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x90 ; MADC = 16, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 16000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24
reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x01 ; DOSR = 384 (MSB)
reg[ 0][ 14] = 0x80 ; DOSR = 384 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0x98 ; MADC = 24, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 11025)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=16
reg[ 0][ 6] = 0x10 ; P=1, R=1, J=16
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x02 ; DOSR = 512 (MSB)
reg[ 0][ 14] = 0x00 ; DOSR = 512 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0xa0 ; MADC = 32, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

%%if (%%prop(SampleRate) == 8000)
reg[ 0][ 5] = 0x91 ; P=1, R=1, J=24
reg[ 0][ 6] = 0x18 ; P=1, R=1, J=24
reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
reg[ 0][ 13] = 0x03 ; DOSR = 768 (MSB)
reg[ 0][ 14] = 0x00 ; DOSR = 768 (LSB)
reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
reg[ 0][ 19] = 0xb0 ; MADC = 48, divider powered on
reg[ 0][ 20] = 0x80 ; AOSR = 128
reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
%%endif

Hi, David,

So, are you using PurePath Studio in order to use the EVM or are you using the CodecControl program? Also, do you have any information about the WCLK frequency?

Best regards,
Luis Fernando Rodríguez S.

This is exactly what I am doing:

1) Plug the EVM module into PC using USB cable. 

2) Connect "HP Out" to my audio amplifier using 3.5mm stereo jack. The amplifier has 26db of gain. The speaker has around 83db efficiency. The amplifier is a dev board with very low noise on its own. 

3) Select "USB-AudioEVM" as my default playback device in windows. 

4) Open "CodecControl" program

5) View - Command - Open "AIC3120_USB_Init.txt"

6) Run

The EVM boots up and starts playing back audio from the PC. However, there is a very loud hiss noise in the speaker. This is my problem - if I can't remove this hiss then this codec is not usable to us. It is too noisy. 

It sounds like soft high frequency white noise which "pumps" slightly. You can hear it when you plug headphones into the EVM also. Here is a screenshot of the HP out on my scope. You can see how noisy it is. 

Obviously, this isn't right. I also have the AIC3254 EVM and this has a clean output with nowhere near as much noise. So it's either:

1) This codec is noisy and we can't use it for our application

2) It isn't set up correctly

3) I have a faulty EVM board. 

I have tried a few things:

1) Disconnecting the DAC output from the HP out eliminates the noise (and the audio of course)

2) Reducing the DVol does not reduce the noise

3)  Reducing the "analog attenuation" does reduce the noise. 

So I'm guessing the noise is being created in the DAC. 

Can you please grab an AIC3120EVM and follow my steps above and see if you get the same results. Thank you. In the meantime I will check the clock configuration. 

In the meantime I will check the clock configuration. 

Hi, David,

This kind of problems are often related with the PLL/dividers configuration. If MCLK is configured as 11.2896MHz, then you should to ensure that the sampling frequency is being configured correctly.

I suggest to modify the Init file to disable the PLL and use only the dividers.

Could you try to use N = 2, M = 1 and DOSR = 128? This will result in a sampling frequency of 44.1kHz.

Please let me know if the problem persists.

Best regards,
Luis Fernando Rodríguez S.

I tried this. I managed to set it up exactly like that using the cc gui. It made no difference to the noise.

Can you grab an evm and copy what im doing please?

Hi, please can you grab an EVM and do exactly as I am doing then measure the HP OUT noise... it is quite urgent. 

I need to decide on the codec we will use for our next product. Unless I can achieve low noise with this codec I will have to use a different supplier and part. 

Hi, David,

I already tested the EVM as you said. The loopback mode seems to be really sensitive on this EVM. So, I used an input signal around 500mV (max. value). Then, I needed to use a 40k input resistor and un-route the input CM.

Could you try with this on your EVM, please?

Thank you.

Best regards,
Luis Fernando Rodríguez S.

As I'm not getting any assistance with this I have to abandon using this codec.