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TLV320AIC3204 HPL/HPR distortion

Other Parts Discussed in Thread: TLV320AIC3204, CC8531

Hi all,

Recently I developed a small PCB's with CC85xx, TLV320AIC3204, MCU etc. We finally got things working. However, the audio coming through is a little distorted. I tried a lot of things:
- Increasing the capacitance of C26, C45
- Enabling/disabling the MICBIAS
- Played with the diffent gains and volumes. The distortion varies along with it.

I also have a HEADSET DEV kit available. I programmed these devices to be either the master or slave. When I use my designed master and the dev kit slave the audio is not distorted and sounds very nice. When I use dev kit master and my slave, the audio is distorted. So I suspect the slave, but I don't know where to look and what to do. Please advise.

Bellow a snippet of my schematic showing the implementation of the TLV320AIV3204 on my slave.

Attached you also find my init file and my activation why. You may ask why two, for know this makes no sense, but in a later stadium the initialisation and activation will not follow directly after each other.

WHS_Init_v3.txt
###############################################################
#						WHS Codec Init
#	Version: v3
#	Last changed: 23/05/2016 11am
#	Changed by: MHT
#	Changes: Added revision info, clock (see remark)
###############################################################

# ---- CLOCK SETTINGS ----
# Power up the NDAC divider with value 1
# Power up the MDAC divider with value 2  
# Program OSR for DAC to 128 (MSB)
# Program OSR for DAC to 128 (LSB)
w 30 0B 81 82 00 80
# Power up the NADC divider with value 1
# Power up the MADC divider with value 2  
# Program OSR for ADC to 128    
w 30 12 81 82 80
# ---- END CLOCK SETTINGS ----

# ---- DIGITAL INTERFACE ----
# I2S, 16-bit, BCLK and WCLK are inputs
w 30 1B 00
# ---- END DIGITAL INTERFACE ----

# ---- PROCESSING BLOCK USAGE ----
# Select DAC processing block PRB_P8
w 30 3C 08
# Select ADC processing block PRB_R1
w 30 3D 01
# ---- END PROCESSING BLOCK USAGE ----

# ---- POWER SUPPLYs ----
# Select register page 1
w 30 00 01
# Disable weak internal connection of AVDD with DVDD    
w 30 01 08
# Enable internal analog LDO, analog blocks powered
w 30 02 01
# Common mode set to 0.9V
# Optie 1: D1 0=HPL/HPR via AVDD 1=HPL/HPR via LDOIN
# Optie 2: D0 0=D1 is 1 en range 1,5 to 1,95V 1=D1 is 1 en range 1,8 to 3,6V
w 30 0A 00
# ---- END POWER SUPPLYs ----

# ---- MICPGA DELAY, REFERENCE CHARGING AND HEADPHONE DE-POP ----
# Enable MICBIAS connected to AVDD  and Mic BIAS set to 2,075V (with CM = 0,75)
w 30 33 64
# Set left MICPGA gain +x dB    
#w 30 3B 80
# MICPGA startup delay is 3 ms
w 30 47 31
# Reference charging time is 40 ms
w 30 7B 01
# HP driver power-up: 50 ms soft routing step time, 5.0 time constants, 6k resistance
w 30 14 65
# ---- END MICPGA DELAY, REFERENCE CHARGING AND HEADPHONE DE-POP ----

# ---- AUDIO ROUTING ----
# HPL routing: Left channel's DAC reconstruction filter's positive terminal
w 30 0C 08
# HPR routing: Right channel's DAC reconstruction filter's positive terminal
w 30 0D 08
# IN1L is routed to Left MICPGA with 20K resistance
w 30 34 40
# CM1L is routed to Left MICPGA via CM1L with 20K resistance    
w 30 36 40
# IN1R is routed to Right MICPGA with 10K resistance
w 30 37 40
# CM1R is routed to Right MICPGA via CM1R with 10K resistance
w 30 39 40
# ---- END AUDIO ROUTING ----

# ---- DC FILTER LEFT CHANNEL ----
# Select register page 8
w 30 00 08
w 30 18 7F
w 30 19 FF
w 30 1A 00
w 30 1C 80
w 30 1D 01
w 30 1E 00
w 30 20 7F
w 30 21 FC
w 30 22 00
#                n0 + n1 * z^-1
#     H(z) = ----------------------
#               2^23 - d1 * z^-1
#
# The constants are defined as
#     n0 = 32767 * 256
#     n1 = -32767 * 256
#     d1 = 32768 * 256 * (1- 2^13)
# This gives a filter with cutoff at approx. 1 Hz
# ---- END DC FILTER LEFT CHANNEL ----

# ---- DC FILTER RIGHT CHANNEL ----
w 30 00 09
w 30 20 7F
w 30 21 FF
w 30 22 00
w 30 24 80
w 30 25 01
w 30 26 00
w 30 28 7F
w 30 29 FC
w 30 2A 00
# ---- END DC FILTER LEFT CHANNEL ----


WHS_Activate_v1.txt
###############################################################
#						WHS Codec Activate
#	Version: v1
#	Last changed: 24/05/2016 4pm
#	Changed by: MHT
#	Changes: Added revision info
###############################################################


# Select register page 0 
w 30 00 00
# Power up left ADC channel
# Unmute left ADC channel 
w 30 51 C0 00
# Select register page 1
w 30 00 01
# HPL driver: Unmute, 0 dB gain
w 30 10 00
# HPR driver: Unmute, 0 dB gain
w 30 11 00
# All output drivers powered up
w 30 09 3C
# Select register page 0
w 30 00 00
# Set left DAC digital volume to 0 dB
w 30 40 00
# Power up the DAC channels, normal channel routing, soft-stepping disabled    
w 30 3F D6

Thank you!

  • Hello, Mathieu,

    It should be related with a slave problem as you mentioned. I noticed that LDO_SELECT is connected to a voltage divider (R22 and R23). It is recommended to connect this pin to IOVDD voltage in order to use the internal LDO. Could you try removing the R23 resistor, please?

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis Fernando Rodriguez,


    Sorry for not mentioning it before. But R23 is not stuffed on the PCB layout. Only the footprint is there for flexibility.
    I agree that there is something wrong with the slave. But I unable to find what.

    I've compared my design with the headset reference design. Whet I don't understand is why LDO_SEL is default low and there is no external voltage connected to Avdd, only capacitance for filtering. According to this image in the abstract it should have a supply voltage connected to power the analog blocks.

    King regards
    Mathieu

  • Hi all,

    In meanwhile I did some more testing. I though it would be helpful to visualize the problem, might be easier to understand what is going on.
    While viewing the signals on a scope I noticed that there is a corelation between the audio signal and the distortion.

    The yellow signal is the input signal and the green one measured at the speaker. There is a 50 Ohm speaker connected to the HPL output of the AIC3204.
    The input signal was 85 Hz as you can see at exactly the double of that frequency there is superposed distortion of 170 Hz.
    When I increase the input signal the superposed frequency is increasing too. When playing music this results in a distorted output signal.
    Any suggestion what could cause this behavior?

    Kind regards,

    Mathieu

  • Hi, Mathieu,

    The distortion problems are often related with the clock settings. So, could you provide your clocks frequency values, please?

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • Mathieu,

    Additionally, have you tried to use different processing blocks?

    Best regards,
    Luis Fernando Rodríguez S.
  • Fernando,

    No I haven't tried any other blocks. What do you suggest?
    My clock settings are the same as the master. The CC8531 has a 48MHz crystal and generates a clock signal on the MCLK pin for the audio codec. Refer to WHS_Activate_v1.txt for codec init.

    An other thing which is very odd. I use my MCU to setup the AIC3204 codec while the development kit uses the CC8531. I use the same default configuration as in purepath wireless configurator. And my slave suffers from the distortion and the development kit not.

  • Hi, Mathieu,

    The processing block selection depends of the sample rate that you're using on the codec. So, it is important to know the clock frequencies on the codec. Could you provide the MCLK, BCLK and WCLK frequencies, please? If possible, could you provide the MCLK, BCLK and WCLK frequencies of the development kit too, please?

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Fernando,


    The dev kit and my setup are configured the same way. That is what makes it odd.

    MCLK (generated by CC8531): 11,2896 MHz

    BCLK: 2,8224 MHz

    WCLK: 44,1 kHz

    NDAC: 1 ; MDAC: 2 ; DOSR: 128


    Kind regards,

    Mathieu

  • Hi, Mathieu,

    Could you try using the ADC processing blocks PRB_R1, PRB_R2 and PRB_R3 and DAC processing blocks PRB_P1, PRB_P2, PRB_P3, PRB_P23 and PRB_P24, please? This is only to ensure that it is not related with a software problem.

    Additionally, it could be related with a digital I/O issue. I noticed that your board is using 2.85V at IOVDD. So, does the dev kit use the same voltage levels than your board? I mean, are the digital I/O signals at same level?

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis Fernando,

    Sorry for my late reply, but I had other priorities. Now I'm back on the audio issue. Unfortunately no further progress. I'm still in the dark.

    - I tested different processing block, this did not resolve the issue. The audio quality was slightly different when I switched to other blocks, but none of them resolved the issue.

    - I use different I/o levels depending on the board. Master 3,3V (5V step-down), Slave 2,85V (battery powered), Dev kit default  2,85V (Battery powered). FYI battery charger/DCDC is the same as on the development kit only the output voltage differs because I  needed a hight voltage rail for some other components. These boards are physically not connected to each other.

    - I also verified the clock signals with my oscilloscope. And they are a bit noise, but within spec I guess. See for yourself:

    MCLK

    BCLK

    WCLK

    Also I spotted a small difference between my slave and the development kit. Unfortunately I'm unable to modify my PCB since the connection is made bellow the chip package. I do not have the tools to remove a VQFP and to position it back.

    Development kit:

    My slave:

    Any Idea's?

  • Hi, Mathieu,

    Could you try configuring the PLL to get the sampling rate? This is to isolate the problem and to know if this is related with the sampling rate generation.

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,


    I setup the PLL like the image bellow. The BCLK and WCLK are still inputs. I use MCLK to generate the internal signals. Unfortunately the problem persists. MADC NADC and AOSR remained the same.

    # ---- CONFIGURE PLL ----
    # R = 1 ; P = 4 ; J = 4 ; D = 0
    w 30 04 03 41 04 00 00
    #PLL ON
    w 30 05 C1
    # ---- END CONFIGURE PLL ----
    
    # ---- CLOCK SETTINGS ----
    # Power up the NDAC divider with value 1
    # Power up the MDAC divider with value 2  
    # Program OSR for DAC to 128 (MSB)
    # Program OSR for DAC to 128 (LSB)
    w 30 0B 81 82 00 80
    # Power up the NADC divider with value 1
    # Power up the MADC divider with value 2  
    # Program OSR for ADC to 128    	
    w 30 12 81 82 80
    # ---- END CLOCK SETTINGS ----

  • In meanwhile with the help of a friend I was able to replace the TLV320AIC3204 and cut the AGND trace connected to IOVSS and made a wire connection to the digital GND.
    Again this did not resolve the issue.
  • Hi, Mathieu,

    Thank you for test with the PLL values. Is it possible to try with another two tests?

    - Could you try changing the HP Power Source from AVDD to LDOIN (1.8V to 3.6V) with Page 1 / Register 10?
    - Could you try using a different processing block for the DAC functions (Page 0 / Register 60)? Some of the processing blocks have more capabilities than others.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis,

    I've tried the suggested things. Still no progress.
    The distortion changed with the selected processing block. The audio quality was wore when I selected a block with less resources.
    Any other suggestions?
    In parallel I'm doing some manual lay out changes to see if that influences the behavior. For now still no luck.
    I'm getting out of idea's here...

    This afternoon I went through a few topic on the e2e forum. I found an interesting problem and I'm wondering if it could be related.
    Refer to one of the last posts of kjetil: https://e2e.ti.com/support/wireless_connectivity/purepath_wireless/f/382/t/203770#pi239031350=1

    The problem was resolved by changing something with the NWM_ACH_SET_USAGE EHIF command. I was unable to find the NVM_ACH_SET_USAGE_EHIF in my TI Configurator setup.

    To be clear, in my setup the C8531 is running host-controlled by a MCU. The codec's I2S audio is coming from the C8531 and the codec is setup by the MCU (not the C8531).

    MCU -- SPI --> C8531
       |                        |
       |                      I2S
       |                        |
       |___ I2C ___> Codec

  • Hi luis,

    In addition to my previous post:

    The CC85xx problem I referred to got me thinking, what if the I2S data is wrong. That would explain why changing something in the codec would not affect the problem.

    I've started measuring the I2S data with a logic analyzer. And in fact, every 128 samples (frequency is aprox 344 Hz with fs=44,1kHz), there are two samples missing (I suppose 1 left and 1 right). See for yourself on the scope plots.

    I also tried to increase the sample frequency to see what affects the drop out. And the frequency of occurrence varies along with the sample frequency, for 48 kHz it was 374Hz. When I looked in to it I noticed that it occurs every 128 periods of WCLK.

    Plot showing the occurrence:

    Plot showing the missing data:

    Plot showing the dip on the audio signal:

    I played around with the time slot value's, unfortunately it only varies it between 3500 and 3750 µs. The C8531 is set to 2Mbit in mode A. with 3750 µs timeslot. Audio is set to 44,1kHz SLAC with 1984 samples latency.

    And still, when I configure the dev handset kit to match my setup I'm able to listen without any distortion/sample drop. Only difference is that my setup is host controlled and the devkit still is autonomous mode.

    Any suggestions on how to resolve this issue?

  • Hi all,


    I like to inform you that the problem is solved.

    When I read previous mentioned E2E post, I started thinking about "What is the CC8531 is wrong instead of the 320AIC3204 codec?". Then I read the throubleshouting help section of the PurePath Wirelles configurator and I found this suspicious line:

    Poor Audio Quality
    
    Audio is heavily distorted in host-controlled operation, but OK in autonomous operation: Verify parameters used in the NWM_ACH_SET_USAGE EHIF command.


    This matched my problem description, so I started looking into the EHIF command. And in fact, the parameter value was set incorrectly. When set to the correct channel (Primary/Fron Left) the audio distortion was gone.
    I have no Idea why there even was audio since the parameter indicates which channel to listen to, but now its fine.