Hi all,
Recently I developed a small PCB's with CC85xx, TLV320AIC3204, MCU etc. We finally got things working. However, the audio coming through is a little distorted. I tried a lot of things:
- Increasing the capacitance of C26, C45
- Enabling/disabling the MICBIAS
- Played with the diffent gains and volumes. The distortion varies along with it.
I also have a HEADSET DEV kit available. I programmed these devices to be either the master or slave. When I use my designed master and the dev kit slave the audio is not distorted and sounds very nice. When I use dev kit master and my slave, the audio is distorted. So I suspect the slave, but I don't know where to look and what to do. Please advise.
Bellow a snippet of my schematic showing the implementation of the TLV320AIV3204 on my slave.
Attached you also find my init file and my activation why. You may ask why two, for know this makes no sense, but in a later stadium the initialisation and activation will not follow directly after each other.
############################################################### # WHS Codec Init # Version: v3 # Last changed: 23/05/2016 11am # Changed by: MHT # Changes: Added revision info, clock (see remark) ############################################################### # ---- CLOCK SETTINGS ---- # Power up the NDAC divider with value 1 # Power up the MDAC divider with value 2 # Program OSR for DAC to 128 (MSB) # Program OSR for DAC to 128 (LSB) w 30 0B 81 82 00 80 # Power up the NADC divider with value 1 # Power up the MADC divider with value 2 # Program OSR for ADC to 128 w 30 12 81 82 80 # ---- END CLOCK SETTINGS ---- # ---- DIGITAL INTERFACE ---- # I2S, 16-bit, BCLK and WCLK are inputs w 30 1B 00 # ---- END DIGITAL INTERFACE ---- # ---- PROCESSING BLOCK USAGE ---- # Select DAC processing block PRB_P8 w 30 3C 08 # Select ADC processing block PRB_R1 w 30 3D 01 # ---- END PROCESSING BLOCK USAGE ---- # ---- POWER SUPPLYs ---- # Select register page 1 w 30 00 01 # Disable weak internal connection of AVDD with DVDD w 30 01 08 # Enable internal analog LDO, analog blocks powered w 30 02 01 # Common mode set to 0.9V # Optie 1: D1 0=HPL/HPR via AVDD 1=HPL/HPR via LDOIN # Optie 2: D0 0=D1 is 1 en range 1,5 to 1,95V 1=D1 is 1 en range 1,8 to 3,6V w 30 0A 00 # ---- END POWER SUPPLYs ---- # ---- MICPGA DELAY, REFERENCE CHARGING AND HEADPHONE DE-POP ---- # Enable MICBIAS connected to AVDD and Mic BIAS set to 2,075V (with CM = 0,75) w 30 33 64 # Set left MICPGA gain +x dB #w 30 3B 80 # MICPGA startup delay is 3 ms w 30 47 31 # Reference charging time is 40 ms w 30 7B 01 # HP driver power-up: 50 ms soft routing step time, 5.0 time constants, 6k resistance w 30 14 65 # ---- END MICPGA DELAY, REFERENCE CHARGING AND HEADPHONE DE-POP ---- # ---- AUDIO ROUTING ---- # HPL routing: Left channel's DAC reconstruction filter's positive terminal w 30 0C 08 # HPR routing: Right channel's DAC reconstruction filter's positive terminal w 30 0D 08 # IN1L is routed to Left MICPGA with 20K resistance w 30 34 40 # CM1L is routed to Left MICPGA via CM1L with 20K resistance w 30 36 40 # IN1R is routed to Right MICPGA with 10K resistance w 30 37 40 # CM1R is routed to Right MICPGA via CM1R with 10K resistance w 30 39 40 # ---- END AUDIO ROUTING ---- # ---- DC FILTER LEFT CHANNEL ---- # Select register page 8 w 30 00 08 w 30 18 7F w 30 19 FF w 30 1A 00 w 30 1C 80 w 30 1D 01 w 30 1E 00 w 30 20 7F w 30 21 FC w 30 22 00 # n0 + n1 * z^-1 # H(z) = ---------------------- # 2^23 - d1 * z^-1 # # The constants are defined as # n0 = 32767 * 256 # n1 = -32767 * 256 # d1 = 32768 * 256 * (1- 2^13) # This gives a filter with cutoff at approx. 1 Hz # ---- END DC FILTER LEFT CHANNEL ---- # ---- DC FILTER RIGHT CHANNEL ---- w 30 00 09 w 30 20 7F w 30 21 FF w 30 22 00 w 30 24 80 w 30 25 01 w 30 26 00 w 30 28 7F w 30 29 FC w 30 2A 00 # ---- END DC FILTER LEFT CHANNEL ----
############################################################### # WHS Codec Activate # Version: v1 # Last changed: 24/05/2016 4pm # Changed by: MHT # Changes: Added revision info ############################################################### # Select register page 0 w 30 00 00 # Power up left ADC channel # Unmute left ADC channel w 30 51 C0 00 # Select register page 1 w 30 00 01 # HPL driver: Unmute, 0 dB gain w 30 10 00 # HPR driver: Unmute, 0 dB gain w 30 11 00 # All output drivers powered up w 30 09 3C # Select register page 0 w 30 00 00 # Set left DAC digital volume to 0 dB w 30 40 00 # Power up the DAC channels, normal channel routing, soft-stepping disabled w 30 3F D6
Thank you!