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Hi, we are using TLV320 AIC3254. Problem is that external applied analog input IN1_L and IN1_R are getting routed to HPL and HPR even though registers: 0x01 / 0x0C (P1_R12) =0x08 and 0x01 / 0x0D (P1_R13)=0x08.

Other Parts Discussed in Thread: TLV320AIC3254

Hi,

we are using TLV320 AIC3254. Below is the registers configuration for HPL and HPR.The Problem is that when we apply external analog input to IN1_L and IN1_R,  IN1_L/IN1_R are getting routed to HPL and HPR even though we are not routing. We are routing only DAC to HPL/R. If the applied external analog input signal volume level is >50% on the volume bar, huge noise and applied analog audio song is seen on HPL&HPR. could please suggest the missing configuration to avoid internal analog loopback & noise.

Below is the register configuration:

Page 1 / Register 12: HPL Routing Selection Register - 0x01 / 0x0C (P1_R12)=0x08

Page 1 / Register 13: HPR Routing Selection Register - 0x01 / 0x0D (P1_R13)=0x08

Registers and config values written in sequence:


    aic32x4_write_hacked(codec,    0x00    ,    0x00    );
    aic32x4_write_hacked(codec,    0x01    ,    0x01    );

    aic32x4_write_hacked(codec,    0x0c    ,    0x81    );
    
    aic32x4_write_hacked(codec,    0x0d    ,    0x00    );
    // 32-bit(2-channel)
    aic32x4_write_hacked(codec, 0x0e    ,    0x20    );

    // bit clock divider
    aic32x4_write_hacked(codec,    0x1e    ,    0x81    );

    // bit clock divider
    //aic32x4_write_hacked(codec,    0x1e    ,    0x00    );
    
    //bclk-wclk = output to codec
    //aic32x4_write_hacked(codec,    0x1b    ,    0x0c    );
    //bclk-wclk = input to codec
    //aic32x4_write_hacked(codec,    0x1b    ,    0x00    );
    //32 bit
    //aic32x4_write_hacked(codec,    0x1b    ,    0x30    );
        
    //24 bit
    aic32x4_write_hacked(codec, 0x1b    ,    0x20    );

    aic32x4_write_hacked(codec, 0x04    ,    0x10    );

    aic32x4_write_hacked(codec,    0x3c    ,    0x08    );
                    
    aic32x4_write_hacked(codec,    0x00    ,    0x01    );
    aic32x4_write_hacked(codec,    0x01    ,    0x08    );
    aic32x4_write_hacked(codec,    0x02    ,    0x01    );
    aic32x4_write_hacked(codec,    0x7b    ,    0x01    );
    aic32x4_write_hacked(codec,    0x14    ,    0x25    );
    aic32x4_write_hacked(codec,    0x0a    ,    0x00    );
    aic32x4_write_hacked(codec,    0x0c    ,    0x08    );  ==>  page 1 / Register 12: HPL Routing Selection Register - 0x01 / 0x0C (P1_R12)=0x08
    aic32x4_write_hacked(codec,    0x0d    ,    0x08    ); ==>  Page 1 / Register 13: HPR Routing Selection Register - 0x01 / 0x0D (P1_R13)=0x08
    aic32x4_write_hacked(codec,    0x03    ,    0x00    );
    aic32x4_write_hacked(codec,    0x04    ,    0x00    );
    aic32x4_write_hacked(codec,    0x10    ,    0x00    );
    aic32x4_write_hacked(codec,    0x11    ,    0x00    );
    aic32x4_write_hacked(codec,    0x09    ,    0x30    );
    //mdelay(1000 * 3);
    aic32x4_write_hacked(codec,    0x00    ,    0x00    );
    aic32x4_write_hacked(codec,    0x3f    ,    0xd6    );
    aic32x4_write_hacked(codec,    0x40    ,    0x00    );

Thanks and Regards

srinivasa

  • Hello, Srinivasa,

    Welcome to E2E and thank you for your interest in our products!

    I didn't find anything related with a possible route of IN1 to HP output on your register configuration. However, I suggest to mute the IN1 to HP output bypass with page 1 / register 22-23. This will ensure that the input signal is not routed internally.

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis Fernando,

    Thanks for you quick reply. I set page 1 / register 22-23 registers to MUTE=0x75 and then did Self clearing software reset to 0x01 in page 0/Register 1=>0x00 / 0x01 (P0_R1)=0x01 then I did not see noise on HPL/R and IN1_L/R lines also not routed to HPL/R. Setting alone page 1/register 22-23 to MUTE is not helping. Is it the proper way to set page 1 / register 22-23 to MUTE and then apply s/w reset.

    Thanks and Regards

    srinivasa

  • Hi, Srinivasa,

    That's correct. It is the proper way to mute the page 1 / register 22-23 and apply the SW reset.

    I recommend to take a look at the following application report: www.ti.com/.../slaa404c.pdf . It explains the best way to configure and program the TLV320AIC32x4. Noise/Pops problems are often related with the register programming sequence.

    Please let me know if you have more questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis  Fernando,

    I have configured the ADC setup as below, registers and values are loaded as per slaa404c.pdf  page 25. ADC Channel Scripts D.1
    Configure the ADC Channel for Single-ended Stereo Operation. But, ADC out on pin DOUT/MFP2 is not seen. I have applied the external analog input on IN1_L and IN1_R and trying to probe I2S out on DOUT/MFP2, but I2S output is not seen. Is there any thing missing in the below configuration?. Could please let me know what else can be probed like power control.

    ADC setup:

    # Configure ADC Channel
    ###############################################
    #
    # Select Page 1
    >>register 0 = 0x01
    #
    # Route IN1L to LEFT_P with 20K input impedance
    >>Page 1 / Register 52 =0x80


    # Route CM1L to LEFT_M with 20K input impedance

    >>Page 1 / Register 54 =0x80

    # Route IN1R to RIGHT_P with 20K input impedance
    w 30 37 80

    >>page 1/ Register 55 =0x80


    #
    # Route CM1R to RIGHT_M with 20K input impedance
    w 30 39 80

    >>page 1/ Register 57 =0x80
    #
    # Unmute Left MICPGA, Gain selection of 6dB to
    # make channel gain 0dB, since 20K input
    # impedance is used single ended
    w 30 3b 0c

    >>page 1/ Register 59 =0x0C

    #
    # Unmute Right MICPGA, Gain selection of 6dB to
    # make channel gain 0dB, since 20K input
    # impedance is used single ended
    w 30 3c 0c

    >>Page 1 / Register 60=0x0C
    #
    # Select Page 0
    w 30 00 00

    >>Register 0=0x00
    #
    # Power up LADC/RADC
    w 30 51 c0

    >>Page 0 / Register 81 = 0xC0
    #
    # Unmute LADC/RADC
    w 30 52 00

    >>Page 0 / Register 82 = 0x00

    ==========================

    Below is i2c cmd sequence used to load values in sequence for above described ADC setup:

    i2ccmd w 0x18 0x00 0x01 0x01 &

    i2ccmd w 0x18 0x34 0x01 0x80 &

    i2ccmd w 0x18 0x36 0x01 0x80 &


    i2ccmd w 0x18 0x37 0x01 0x80 &

    i2ccmd w 0x18 0x39 0x01 0x80 &  

    i2ccmd w 0x18 0x3B 0x01 0x0C &

    i2ccmd w 0x18 0x3C 0x01 0x0C &

    i2ccmd w 0x18 0x00 0x01 0x00 &

    i2ccmd w 0x18 0x51 0x01 0xC0 &

    i2ccmd w 0x18 0x52 0x01 0x00 &

    Thanks and regards

    srinivasa
     

  • Hi, Srinivasa,

    This is only the ADC setup. There are many registers that must be configured too. Please take a look at the following code lines as a reference. They must be added before the ADC setup.

    ###############################################
    # Software Reset
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Initialize the device through software reset
    w 30 01 01
    #
    ###############################################



    ###############################################
    # Clock Settings
    # ---------------------------------------------
    # The codec receives: MCLK = 11.2896 MHz,
    # BLCK = 2.8224 MHz, WCLK = 44.1 kHz
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # NADC = 1, MADC = 2
    w 30 12 81 82
    #
    ###############################################



    ###############################################
    # Signal Processing Settings
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Set the ADC Mode to PRB_P1
    w 30 3d 01
    #
    ###############################################



    ###############################################
    # Initialize Codec
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # Disable weak AVDD in presence of external
    # AVDD supply
    w 30 01 08
    #
    # Enable Master Analog Power Control
    w 30 02 00
    #
    # Select ADC PTM_R4
    w 30 3d 00
    #
    # Set the input powerup time to 3.1ms (for ADC)
    w 30 47 32
    #
    # Set the REF charging time to 40ms
    w 30 7b 01
    #
    ###############################################

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis Fernando,

    I have done complete procedure mentioned in 4.0.4 Stereo ADC with 48ksps Sample Rate and High Performance in slaa408a.pdf. Below is the procedure I have configured before ADC setup, but still I2S DOUT is not seen on DOUT/MFP2.I am wondering  what is missing.

    # Initialize to Page 0
    w 30 00 00
    # S/W Reset to initialize all registers
    w 30 01 01
    # Power up NADC divider with value 1
    w 30 12 81
    # Power up MADC divider with value 2
    w 30 13 82
    # Program OSR for ADC to 128
    w 30 14 80
    # Select ADC PRB_R1
    w 30 3d 01
    # Select Page 1
    w 30 00 01
    # Disable Internal Crude AVdd in presence of external AVdd supply or before
    # powering up internal AVdd LDO
    w 30 01 08
    # Enable Master Analog Power Control
    w 30 02 00
    # Set the input common mode to 0.9V
    w 30 0a 00
    # Select ADC PTM_R4
    w 30 3d 00
    # Set MicPGA startup delay to 3.1ms
    w 30 47 32
    # Set the REF charging time to 40ms
    w 30 7b 01
    # Route IN1L to LEFT_P with 20K input impedance
    w 30 34 80
    # Route Common Mode to LEFT_M with impedance of 20K
    w 30 36 80
    # Route IN1R to RIGHT_P with input impedance of 20K
    w 30 37 80
    # Route Common Mode to RIGHT_M with impedance of 20K
    w 30 39 80
    # Unmute Left MICPGA, Gain selection of 6dB to make channel gain 0dB
    # Register of 6dB with input impedance of 20K => Channel Gain of 0dB
    w 30 3b 0c
    # Unmute Right MICPGA, Gain selection of 6dB to make channel gain 0dB
    # Register of 6dB with input impedance of 20K => Channel Gain of 0dB
    w 30 3c 0c
    # Select Page 0
    w 30 00 00
    # Power up Left and Right ADC Channels

    w 30 51 c0
    # Unmute Left and Right ADC Digital Volume Control.
    w 30 52 00

    Then used ADC setup, but I2S out is not seen.

    Thanks and Regards

    srinivasa

  • Hello, Srinivasa,

    I already verified your register settings. It is correct and you should be able to see the I2S output.

    So, the next step would be verify if the I2S clocks are correct. Could you verify the WCLK and BCLK signals? Additionally, could you verify the power sources? Are the voltage levels as expected?

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi Luis Fernando,

    I2S clocks BCLK=2.8MHz, WCLK/LRCK=44.1KHz MCLK=22.576MHz are input to the codec, configured as I2S, 24bit format. MCLK pin is CODEC_CLKIN. NADC=1, MADC=2 AOSR=128. As per ADC_fs=CODEC_CLKIN/(NADCxMADCxAOSR), is it necessary to take MADC=4 so as to equate ADC_fs=44.1khz ?.

    AVdd=1.718V, DVdd=1.718V. Page 1 / Register 2: LDO Control Register - 0x01 / 0x02 (P1_R2)=0x01. AVDD LDO Control[D5-D4] bits=00. Common Mode is 0.9V. seems voltage levels are as expected.

    Thanks and Regards
    srinivasa
  • Hi Luis Fernando,

    I have made below observations for TLV320AIC3254, could you please make your time convenient to reply.

    1. If   Page 1 / Registers 22-23 set to MUTE, to mute the IN1L/R to HPL/R and then apply s/w reset, noise is reduced but all registers are reset to default. Is there any way to MUTE the IN1L/R to HPL/R without applying s/w reset.

    2. If page 1/ Register 2, LDO Control Register- over current detection is set to 0x01 then noise and external applied analog IN1_L/R are heared on HPL/R as if it is like analog loopback in codec. If over current detection is set to 0 then no noise, no IN1_L/R to HPL/R and no DAC output is seen on HPL/R. If both DAC&ADC should work means what could be configuration.

    3. BCLK=2.8MHz, WCLK/LRCK=44.1KHz MCLK=22.576MHz are input to the codec configured I2S, 24bit format. MCLK pin is CODEC_CLKIN. NADC=1, MADC=2 AOSR=128. As per ADC_fs=CODEC_CLKIN/(NADCxMADCxAOSR) I have changed MADC=4 but still I2S DOUT is not seen on OUT/MFP2.

    AVdd=1.718V, DVdd=1.718V. Page 1 / Register 2: LDO Control Register - 0x01 / 0x02 (P1_R2)=0x01. AVDD LDO Control[D5-D4] bits=00. Common Mode is 0.9V.

    Thanks and Regards

    srinivasa

  • Hi, Srinivasa,

    Thank you for your observations. These results make me think that the problem is related with the power supplies. Could you provide more information related with the power pins? Are AVDD and DVDD being applied by an external source? The LDO is enabled, so it is only necessary to apply IOVDD and LDOIN. Please take a look at the following document for details:

    www.ti.com/.../slaa492a.pdf

    Best regards,
    Luis Fernando Rodríguez S.
  • Hi, Luis Fernando Rodriguez S,

    Thanks for your reply.

    AVDD and DVDD are being generated by an internal LDO. The LDO is enabled in Page 1 / Register 2: LDO Control Register - 0x01 / 0x02 (P1_R2)=  0x01. 1: AVDD LDO Powered up.   Only external 3.283v applied to IOVDD, LDOIN and LDO_ SELECT.   AVDD and DVDD values=1.717V internally generated properly. Reset=3.283V.

    TLV320AIC3254 codec is in slave mode receiving I2S clocks from Master. Configuring both DAC&ADC of the codec to receive external analog input on IN1_L/R and to playback on HPL/R by Master. Only Playback from Master is fine, DAC is working as expected.  For recording and playback ADC is not working, I2S out on DOUT/MFP2 is not seen.

    Thanks and Regards

    srinivasa

  • Hi, Luis Fernando,

    Thanks for your reply, Hope I have updated below information related to power control.

    AVDD and DVDD are being generated by an internal LDO.

    The LDO is enabled in Page 1 / Register 2: LDO Control Register - 0x01 / 0x02 (P1_R2)=  0x01. 1: AVDD LDO Powered up.  

    Only external 3.283v applied to IOVDD, LDOIN and LDO_ SELECT.

    AVDD=1.717V and DVDD =1.717V internally generated properly. Reset=3.283V.

    TLV320AIC3254 codec is in slave mode receiving I2S clocks from Master. Configuring both DAC&ADC of the codec to receive external analog input on IN1_L/R and to playback on HPL/R by Master. Only Playback from Master is fine, DAC is working as expected.  For recording and playback ADC is not working, I2S out on DOUT/MFP2 is not seen.

    Here my question is that, is there any limitation in codec it should not provide I2S out on DOUT/MFP2 in slave mode in the case where in codec is receiving clocks from Master.

    Thanks and Regards

    srinivasa

  • Hi, Srinivasa,

    There are few reasons that could be related with this problem, even if the clocks are generated from the master:

    - There could be an AVDD issue (a damage, for example, since it is generated by the AVDD LDO).
    - ADC sampling rate is not being configured.
    - ADC/PGA is not enabled.
    - DOUT pin is not being enabled (page 0 / register 53).

    Could you verify all these reasons?

    Please let me know if the problem persists.

    Best regards,
    Luis Fernando Rodríguez S.