How to get the EQ setting in PPS

Hi, iehncent,

The register address can be located in the properties window of the biquad block. See the following picture for details:

So, you may find the information about the registers in your code. Search for page 11 (0x0b). Then, search the I2C register 72 (0x48). You will see all the coefficients values (see red circle above).

Best regards,
Luis Fernando Rodríguez S.

Hi Sir,

Thanks for your support.
We had wirte these EQ setting, but don't have difference at these file.
Need turn on these EQ?

Hi, iehncent,

Could you re-make your entire PPS process flow? Sometimes PPS doesn't respond correctly when the blocks are copied from another PPS process flow. We suggest to configure your algorithm from the beginning. You probably will see that the EQ block has been assigned to another I2C register. Additionally, there's no need to turn on the EQ.

Best regards,
Luis Fernando Rodríguez S.

Hi Sir,

We had use the .h file ( as attached file ) for our board, it don't have sound, need change the  reg[  0][ 60] from 0x00 to 0x01.

# reg[  0][ 60] = 0x00 ; Use miniDSP_D for signal processing

We had used the AP to do the frequency response, but don't have EQ, could you help us to check it?

Why need change the 60 from 00 to 01, but EVM is use the 00.

Thanks!base_main_Rate48_pps_driver.h

Hi, iehncent,

I tested your EQ.pfw files with the TLV320AIC3254EVM and they seem to work correctly. The biquad filters are applied as expected. Please ensure that the hex values from the biquad properties window are applied to the .c files as I mentioned in previous posts. Additionally, it seems that your base_main_Rate48_pps_driver.h doesn't contain information.

Best regards,
Luis Fernando Rodríguez S.

Hi Sir,

Thanks you for your support.
We use the LAM for host in our board, the MCLK is 6.144MHz, LRCLK is 48KHz, 24bit.
How to setting the PLL

Hi, iehncent,

For the clock values that you're using, the codec doesn't require PLL. You may use only the dividers as NADC = MADC = NDAC = MDAC = 1 and AOSR = DOSR = 128.

6.144MHz / 128 = 48KHz.

Best regards,
Luis Fernando Rodríguez S.

Hi Sir,

So I don't need setting the CS tool ( Codec Clock/PLL ) right?

Only setting CS tool ( Dividers ) MADC = NDAC = MDAC = 1 and AOSR = DOSR = 128 and power on them, right?

Thanks!

Hi,

That's correct. For your purposed clock values, there's no need to configure the Codec Clock / PLL. You only require to configure the dividers as you mentioned.

Best regards,
Luis Fernando Rodríguez S.

Hi Sir,

Thanks for your support. we
Before we had setting the PLL, R=1 P=1 J.D=14.0000 MDAC/MADC=2 NDAC/NADC=7 AOSR/DOSR=128
But have frequency response issue, if I2S input over 12KHz..13K..14K.. the output will be 8Khz..7K...6K.., it was normal before 12KHz.
Do you think it is clock issue?

Hi,

This could be related with a clock issue. We can ensure that if you only configure the dividers instead the PLL. The PLL requires more considerations. Please take a look at the 2.7.1 PLL section for details.

Best regards,
Luis Fernando Rodríguez S.