PCM5100A / SCK frequency tolerance

K.Yaita

Other Parts Discussed in Thread: PCM5100A

Hi Team,

The datasheet shows the three digits after the decimal point for SCK[MHz] frequency.
Is there requirement of SCK frequency tolerance if using external SCK?

Best Regards,
Yaita / Japan disty

over 7 years ago

0 Pavel Ruzicka over 7 years ago

Expert 1720 points

Hi,
In datasheet in point 9.3.5.2 is described supported tolerance +/- 4% of sample frequency. All other signals like BCK, DATA and SCK are always synchronized together with LRCK. Always it is a good idea to have low-jitter I2S clock signals.

0 Justin Bohr over 7 years ago in reply to Pavel Ruzicka

TI__Mastermind 27850 points

Hi Kensuke,

Pavel is correct in the tolerance for the MCLK to LRCK, and the table you copied is showing MCLKs for standard audio rates. If you are not concerned with the sampling rate being standard, and the I2S clocks are synchronous, then the part will still operate. For example a 12 MHz MCLK, with a 46.875 kHz LRCK and a BCK of 6 MHz will work just fine.

Justin

0 K.Yaita over 7 years ago in reply to Justin Bohr

Guru 29690 points

Hi Justin-san,

I appreciate for your support.

>For example a 12 MHz MCLK, with a 46.875 kHz LRCK and a BCK of 6 MHz will work just fine.
I believe BCK is 128 x fs in this case and it seems PCM5100A doesn't support it.
Is my understanding correct?

Best Regards,
Yaita

0 Justin Bohr over 7 years ago in reply to K.Yaita

TI__Mastermind 27850 points

Hi Yaita-san,

You are correct, I should have used an example with a 64*Fs BCK.

Justin

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PCM5100A / SCK frequency tolerance