PCM5100A / Table 10

K.Yaita

Hi Team,

Table 10 shows "(2) This system clock rate is supported by PLL mode" as the following, however I couldn't catch what does it indicate.

Does it correlate somewhat with Table 11?

Best Regards,
Yaita / Japan disty

over 7 years ago

0 Pavel Ruzicka over 7 years ago

Expert 1720 points

Hi,

Normally on I2S is used Audio frame 64 bits long for both channels. You can have 16, 24 or 32 bit samples in them. There also exists I2S signals for 16bit samples which use only 32bit frames long or 24bit samples which used 48bit long frames.

Example for Table 11:

CD signal 16bits/44.1kHz:

BCK 64bits: 2.8224MHz

BCK: 48bits: 2.1168MHz

BCK: 32bits: 1.4112MHz

It tells, that when you use 3 wire I2S without SCK signal, that DAC accept BCK 64x, 48x or 32x FS and internally generate SCK 5.6448MHz for BCK 64x and 32x and 8.4672MHz for BCK 48x.

It mean that with BCK64x is used 2x oversampling, with BCK48x 4x and with BCK32x also 4x for 44.1kHz sample frequency.

LRCK is always sample frequency.

I always used BCK 64x FS for all sample frequencies and bit depths.

0 K.Yaita over 7 years ago in reply to Pavel Ruzicka

Guru 29690 points

Hi

I believe (2) of Table 10 indicates internal PLL is used although 4-Wire I2S as the following.
(datasheet page 24)
The device has an internal PLL that is used to take either SCK or BCK and create the higher rate clocks required by the interpolating processor and the DAC clock.

On the other hand, the fsck value that doesn't show (2) indicate internal PLL isn't used. SCK itself is used for the higher rate clocks required by the interpolating processor and the DAC clock.

Is my understanding correct?

Best Regards,
Yaita

0 K.Yaita over 7 years ago in reply to K.Yaita

Guru 29690 points

Hi Team,

Is my understanding correct?

Best Regards,
Yaita

0 Justin Bohr over 7 years ago in reply to K.Yaita

TI__Mastermind 27850 points

Hi Yaita,

For Table 10, the scenarios marked with the (2) are utilizing the PLL to create a faster system clock to allow the part to function correctly with the sampling rate. For table 10, every scenario is using the PLL to create faster system clock.

Justin

0 K.Yaita over 7 years ago in reply to Justin Bohr

Guru 29690 points

Hi Justin-san,

Thank you always for your support.

I would like to confirm just in case.
Is the following yellow part typo for "table 11"?
>For table 10, every scenario is using the PLL to create faster system clock.

Best Regards,
Yaita

0 Justin Bohr over 7 years ago in reply to K.Yaita

TI__Mastermind 27850 points

Hi Yaita-san,

Correct, I apologize, table 11 is what I meant there.

Justin

0 Kenichiro over 6 years ago in reply to Justin Bohr

Mastermind 9165 points

Justin, Pavel,

Can you help me to understand this restriction?

My customer has seen that PCM510xA-Q1 does NOT operate with 128fs(12.288MHz) SCK for 96KHz sampling frequency.

From the description of 3-wire PCM mode, I suppose that the internal PLL is disabled, since customer has SCK input.
So, it means, to support 128fs for 96KHz, it's required to use 3-wire PCM mode (in other words "PLL mode".).

Correct?

Thank you so much for your support.
Regards,
Ken

0 Kenichiro over 6 years ago in reply to Kenichiro

Mastermind 9165 points

Hi Audio Forum Member,

Can anyone take a look and comment on the pose above?

Thank you for your support!
Regards,
Ken

0 Paul_Frost over 6 years ago in reply to Kenichiro

TI__Guru 52683 points

Hi Ken,

I believe you are correct that this is only supported while in PLL mode. I will be checking with our design team to verify.

I hope to get an answer to you tomorrow.

Thanks!

Paul

0 Kenichiro over 6 years ago in reply to Paul_Frost

Mastermind 9165 points

Hi Paul,

Thank you for your support!
I wait for your update.

Regards,
Ken

0 Paul_Frost over 6 years ago in reply to Kenichiro

TI__Guru 52683 points

Hi Ken,

The system clock frequencies denoted with (2) on table 3 of the PDS are only supported by the PCM510X in PLL mode.

Let me know if you have any more questions.

Thanks!

Paul

0 Kenichiro over 6 years ago in reply to Paul_Frost

Mastermind 9165 points

Hi Paul,

What make me confused is not much description of "PLL mode" in the datasheet.
If you say that "PLL mode" means "Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)", then I fully understand.

Thanks,
Ken

0 Paul_Frost over 6 years ago in reply to Kenichiro

TI__Guru 52683 points

Yes, that is what the PDS is trying to say. I do understand the confusion - I checked in the lab to verify!

0 Kenichiro over 6 years ago in reply to Paul_Frost

Mastermind 9165 points

Hi Paul,

Thanks!! It's clear!!

Arigato-
Ken

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PCM5100A / Table 10