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DIX4192 I2C registers issue

gszklo
Prodigy 40 points
Other Parts Discussed in Thread: DIX4192

Hi everyone,

I'm trying to use DIX4192 in an audio broadcast system where we make use of U databit. The circuit is designed so that the main processor receives transmission and reception interrupts from DIX4192. The problem I am facing is that when receiving an interrupt "Receive buffer", the processor starts reading the 48 User data registers from the address 40h of page 1 through I2C interface in multi read mode. In almost 10% of the frames, randomly a left channel register appears with value 00h and the value that should be there appears in the equivalent register of the right channel. p.ex.: the register 4Bh should be 55h but was read as 00h and the 55h byte appears in the 4Ah register.

In order to identify the source of the problem, I setup a GPIO with U databit and using a data analyzer, recorded the frame received and the data was correct.

The problem seems to be really in the state machine of I2C interface and I wonder if it's a known issue and if there is a workaround that allows the use of this device in these conditions.

Thanks,

Gershon

  • 0
    TI__Guru 57800 points

    Hi, Gershon,

    The engineer in charge of the support of the DIX4192 has been notified of your issue and will get back to you soon. 

    Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    TI__Mastermind 27850 points
    Hi Gershon,

    I have heard one other case like this but I was not able to recreate the issue, and therefore do not have a root cause. Is it always the same register that changes value?

    Justin
  • 0
    Prodigy 40 points
    Hi Justin,

    Thanks for the feedback.

    The problem is completely random and we made the following test to identify what happens:
     
    Every frame we write a different buffer of 48 bytes in Udata registers and then immediately read them to compare with what was written and often they do not match.

    We note that the bytes that do not match are always in pairs, positioned at random, one of them wrong kept the value of the previous buffer and the other contains the value that was theoretically written in the first, that is: it seems that the error occurs with the write pointer inside the I2C state machine of the DIX4192.

    Let's suppose I write in registers a buffer with 123456789 and in the next frame I write a buffer with ABCDEFGHJ. When we read the buffer to check the content we randomly encountered situations like these:
    ABCE5FGHJ or ABHDEFG8J.

    Clearly during multiple write process some registers was written in the wrong place.

    Can you understand that?

    Regards,

    Gershon Szklo
    Syspac Eletrônica
    fone: 11-2193-9200
     fax : 11-2193-9220
    gershon@syspac.com.br


  • 0 in reply to gszklo
    TI__Mastermind 27850 points
    Hi Gershon,

    It seems I understand the issue and its results, would it be possible to share your register read and write sequence? It seems you are waiting for the receive buffer interrupt, is there any ever odd behavior with this interrupt?

    Justin
  • 0
    Prodigy 40 points
    Hi Justin,

    In fact we are using the transmit interrupt. In my application, the DIX is configured as follows: The input stream is applied to the DIR, which is redirected to port A, then from A to B via an external delay line and B for the DIT. In this situation the receive and transmit interrupts do not occur together but always with a random slip between them, preventing us from using the receive event to write the output buffer.

    Attached you will find the sequence (dix.c) and the method (i2c.c) modules that run on a F2802x with BIOS.

    Thanks,

    Gershon Szklo
    Syspac Eletrônica
    fone: 11-2193-9200
     fax : 11-2193-9220
    gershon@syspac.com.br